From: lkcl <lkcl@web>
Date: Wed, 12 Apr 2023 17:05:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls010_v1~51
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8098fd4ce17e926846f12d50d9bf0c82c286a8d;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index bff45dcd8..b55e6b767 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -684,7 +684,7 @@ This is to save on both Vector Length (VL of 16 is sufficient) as well as
 complexity in the Hazard Management when context-switching CR fields, as the
 entire batch of 128 CR Fields may be transferred to 8 GPRs with a VL of 16
 and elwidth overriding of 32. Truncation is sufficent, dropping the top 32 bits
-of the Condition Register(s) which are always zero anywy.
+of the Condition Register(s) which are always zero anyway.
 
 # Separate Scalar and Vector Condition Register files