From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 20:54:03 +0000 (+0200)
Subject: SigSpec refactoring: added RTLIL::SigSpec::operator[]
X-Git-Tag: yosys-0.4~483
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f80da7b41dd9c12d3bd65ceab6c0c6748a70a78c;p=yosys.git

SigSpec refactoring: added RTLIL::SigSpec::operator[]
---

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index facd43db4..da3a2661e 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -522,6 +522,9 @@ public:
 
 	int size() const { return width_; }
 
+	RTLIL::SigBit &operator[](int index) { unpack(); return bits_.at(index); }
+	const RTLIL::SigBit &operator[](int index) const { unpack(); return bits_.at(index); }
+
 	void expand();
 	void optimize();
 	RTLIL::SigSpec optimized() const;
@@ -540,7 +543,7 @@ public:
 	void remove_const();
 
 	RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const;
-	RTLIL::SigSpec extract(int offset, int length) const;
+	RTLIL::SigSpec extract(int offset, int length = 1) const;
 
 	void append(const RTLIL::SigSpec &signal);
 	void append_bit(const RTLIL::SigBit &bit);