From: Florent Kermarrec Date: Tue, 26 Feb 2013 22:14:09 +0000 (+0100) Subject: examples: update & simplify X-Git-Tag: 24jan2021_ls180~2575^2~119 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f823d06cf10b133683d8970e69af1140418802dd;p=litex.git examples: update & simplify --- diff --git a/examples/de0_nano/client/test_MiIo.py b/examples/de0_nano/client/test_MiIo.py new file mode 100644 index 00000000..338e09f2 --- /dev/null +++ b/examples/de0_nano/client/test_MiIo.py @@ -0,0 +1,62 @@ +from migScope import trigger, recorder, migIo + +import sys +sys.path.append("../../../") + +from spi2Csr.tools.uart2Spi import * + +#============================================================================== +# P A R A M E T E R S +#============================================================================== +# Bus Width +trig_width = 16 +dat_width = 16 + +# Record Size +record_size = 1024 + +csr = Uart2Spi(1,115200) + +# Csr Addr +MIIO_ADDR = 0x0000 + +# Miscope Configuration +# miIo +miIo0 = miIo.MiIo(MIIO_ADDR, 8, "IO", csr) + +def led_anim0(): + for i in range(10): + miIo0.write(0xA5) + time.sleep(0.1) + miIo0.write(0x5A) + time.sleep(0.1) + +def led_anim1(): + #Led << + for j in range(4): + ledData = 1 + for i in range(8): + miIo0.write(ledData) + time.sleep(i*i*0.0020) + ledData = (ledData<<1) + #Led >> + ledData = 128 + for i in range(8): + miIo0.write(ledData) + time.sleep(i*i*0.0020) + ledData = (ledData>>1) + +#============================================================================== +# T E S T M I G I O +#============================================================================== + +print("- Small Led Animation...") +led_anim0() +time.sleep(1) +led_anim1() +time.sleep(1) + +print("- Read Switch: ",end=' ') +print(miIo0.read()) + + diff --git a/examples/de0_nano/client/test_MiLa_0.py b/examples/de0_nano/client/test_MiLa_0.py new file mode 100644 index 00000000..d687eae8 --- /dev/null +++ b/examples/de0_nano/client/test_MiLa_0.py @@ -0,0 +1,83 @@ +from miscope import trigger, recorder, miIo, miLa +from miscope.tools.truthtable import * +from miscope.tools.vcd import * + +import sys +sys.path.append("../../../") + +from spi2Csr.tools.uart2Spi import * + +#============================================================================== +# P A R A M E T E R S +#============================================================================== +# Bus Width +trig_width = 16 +dat_width = 16 + +# Record Size +record_size = 4096 + +# Csr Addr +MIIO_ADDR = 0x0000 +MILA_ADDR = 0x0200 + +csr = Uart2Spi(1, 115200, debug=False) + +# MiScope Configuration +# miIo0 +miIo0 = miIo.MigIo(MIIO_ADDR, 8, "IO",csr) + +# miLa0 +term0 = trigger.Term(trig_width) +trigger0 = trigger.Trigger(trig_width, [term0]) +recorder0 = recorder.Recorder(dat_width, record_size) + +miLa0 = miLa.MiLa(MILA_ADDR, trigger0, recorder0, csr) + +#============================================================================== +# T E S T M I G L A +#============================================================================== +dat_vcd = [] +recorder0.size(1024) + +def capture(size): + global trigger0 + global recorder0 + global dat_vcd + sum_tt = gen_truth_table("term0") + miLa0.trig.sum.write(sum_tt) + miLa0.rec.reset() + miLa0.rec.offset(0) + miLa0.rec.arm() + print("-Recorder [Armed]") + print("-Waiting Trigger...", end = ' ') + while(not miLa0.rec.is_done()): + time.sleep(0.1) + print("[Done]") + + print("-Receiving Data...", end = ' ') + sys.stdout.flush() + dat_vcd += miLa0.rec.read(size) + print("[Done]") + +print("Capturing Ramp..") +print("----------------------") +term0.write(0x0000,0xFFFF) +csr.write(0x0000, 0) +capture(1024) + +print("Capturing Square..") +print("----------------------") +term0.write(0x0000,0xFFFF) +csr.write(0x0000, 1) +capture(1024) + +print("Capturing Sinus..") +print("----------------------") +term0.write(0x0080,0xFFFF) +csr.write(0x0000, 2) +capture(1024) + +myvcd = Vcd() +myvcd.add(Var("wire", 16, "trig_dat", dat_vcd)) +myvcd.write("test_MiLa_0.vcd") \ No newline at end of file diff --git a/examples/de0_nano/client/test_MiLa_1.py b/examples/de0_nano/client/test_MiLa_1.py new file mode 100644 index 00000000..d5c2beba --- /dev/null +++ b/examples/de0_nano/client/test_MiLa_1.py @@ -0,0 +1,66 @@ +from miscope import trigger, recorder, miIo, miLa +from miscope.tools.truthtable import * +from miscope.tools.vcd import * + +import sys +sys.path.append("../../../") + +from spi2Csr.tools.uart2Spi import * + +#============================================================================== +# P A R A M E T E R S +#============================================================================== +# Bus Width +trig_width = 32 +dat_width = 32 + +# Record Size +record_size = 4096 + +# Csr Addr +MIIO0_ADDR = 0x0000 +MILA1_ADDR = 0x0600 + +csr = Uart2Spi(1, 115200, debug=False) + +# MiScope Configuration +# miIo0 +miIo0 = miIo.MigIo(MIIO0_ADDR, 8, "IO",csr) + +# miLa1 +term1 = trigger.Term(trig_width) +trigger1 = trigger.Trigger(trig_width, [term1]) +recorder1 = recorder.Recorder(dat_width, record_size) + +miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1, csr) + +#============================================================================== +# T E S T M I G L A +#============================================================================== +dat_vcd = [] +recorder1.size(1024) + +term1.write(0x0100005A,0x0100005A) +sum_tt = gen_truth_table("term1") +miLa1.trig.sum.write(sum_tt) +miLa1.rec.reset() +miLa1.rec.offset(256) +miLa1.rec.arm() + +print("-Recorder [Armed]") +print("-Waiting Trigger...", end = ' ') +csr.write(0x0000,0x5A) +while(not miLa1.rec.is_done()): + time.sleep(0.1) +print("[Done]") + +print("-Receiving Data...", end = ' ') +sys.stdout.flush() +dat_vcd += miLa1.rec.read(1024) +print("[Done]") + +myvcd = Vcd() +myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8))) +myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24))) +myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24))) +myvcd.write("test_MiLa_1.vcd") \ No newline at end of file diff --git a/examples/de0_nano/client/test_MigIo.py b/examples/de0_nano/client/test_MigIo.py deleted file mode 100644 index 64c8727c..00000000 --- a/examples/de0_nano/client/test_MigIo.py +++ /dev/null @@ -1,69 +0,0 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * - -import sys -sys.path.append("../../../") - -from migScope import trigger, recorder, migIo -import spi2Csr -from spi2Csr.tools.uart2Spi import * - -#============================================================================== -# P A R A M E T E R S -#============================================================================== -# Bus Width -trig_width = 16 -dat_width = 16 - -# Record Size -record_size = 1024 - -csr = Uart2Spi(1,115200) - -# Csr Addr -MIGIO_ADDR = 0x0000 - -# MigScope Configuration -# migIo -migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr) - -def led_anim0(): - for i in range(10): - migIo0.write(0xA5) - time.sleep(0.1) - migIo0.write(0x5A) - time.sleep(0.1) - -def led_anim1(): - #Led << - for j in range(4): - ledData = 1 - for i in range(8): - migIo0.write(ledData) - time.sleep(i*i*0.0020) - ledData = (ledData<<1) - #Led >> - ledData = 128 - for i in range(8): - migIo0.write(ledData) - time.sleep(i*i*0.0020) - ledData = (ledData>>1) - -#============================================================================== -# T E S T M I G I O -#============================================================================== - -print("- Small Led Animation...") -led_anim0() -time.sleep(1) -led_anim1() -time.sleep(1) - -print("- Read Switch: ",end=' ') -print(migIo0.read()) - - diff --git a/examples/de0_nano/client/test_MigLa_0.py b/examples/de0_nano/client/test_MigLa_0.py deleted file mode 100644 index df8fd7f9..00000000 --- a/examples/de0_nano/client/test_MigLa_0.py +++ /dev/null @@ -1,90 +0,0 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * - -import sys -sys.path.append("../../../") - -from migScope import trigger, recorder, migIo, migLa -from migScope.tools.truthtable import * -from migScope.tools.vcd import * -import spi2Csr -from spi2Csr.tools.uart2Spi import * - -#============================================================================== -# P A R A M E T E R S -#============================================================================== -# Bus Width -trig_width = 16 -dat_width = 16 - -# Record Size -record_size = 4096 - -# Csr Addr -MIGIO_ADDR = 0x0000 -MIGLA_ADDR = 0x0200 - -csr = Uart2Spi(1,115200,debug=False) - -# MigScope Configuration -# migIo0 -migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr) - -# migIla0 -term0 = trigger.Term(trig_width) -trigger0 = trigger.Trigger(trig_width, [term0]) -recorder0 = recorder.Recorder(dat_width, record_size) - -migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr) - -#============================================================================== -# T E S T M I G L A -#============================================================================== -dat_vcd = [] -recorder0.size(1024) - -def capture(size): - global trigger0 - global recorder0 - global dat_vcd - sum_tt = gen_truth_table("term0") - migLa0.trig.sum.write(sum_tt) - migLa0.rec.reset() - migLa0.rec.offset(0) - migLa0.rec.arm() - print("-Recorder [Armed]") - print("-Waiting Trigger...", end = ' ') - while(not migLa0.rec.is_done()): - time.sleep(0.1) - print("[Done]") - - print("-Receiving Data...", end = ' ') - sys.stdout.flush() - dat_vcd += migLa0.rec.read(size) - print("[Done]") - -print("Capturing Ramp..") -print("----------------------") -term0.write(0x0000,0xFFFF) -csr.write(0x0000, 0) -capture(1024) - -print("Capturing Square..") -print("----------------------") -term0.write(0x0000,0xFFFF) -csr.write(0x0000, 1) -capture(1024) - -print("Capturing Sinus..") -print("----------------------") -term0.write(0x0080,0xFFFF) -csr.write(0x0000, 2) -capture(1024) - -myvcd = Vcd() -myvcd.add(Var("wire", 16, "trig_dat", dat_vcd)) -myvcd.write("test_MigLa_0.vcd") \ No newline at end of file diff --git a/examples/de0_nano/client/test_MigLa_1.py b/examples/de0_nano/client/test_MigLa_1.py deleted file mode 100644 index 69c8e203..00000000 --- a/examples/de0_nano/client/test_MigLa_1.py +++ /dev/null @@ -1,73 +0,0 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * - -import sys -sys.path.append("../../../") - -from migScope import trigger, recorder, migIo, migLa -from migScope.tools.truthtable import * -from migScope.tools.vcd import * -import spi2Csr -from spi2Csr.tools.uart2Spi import * - -#============================================================================== -# P A R A M E T E R S -#============================================================================== -# Bus Width -trig_width = 32 -dat_width = 32 - -# Record Size -record_size = 4096 - -# Csr Addr -MIGIO0_ADDR = 0x0000 -MIGLA1_ADDR = 0x0600 - -csr = Uart2Spi(1,115200,debug=False) - -# MigScope Configuration -# migIo0 -migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr) - -# migIla1 -term1 = trigger.Term(trig_width) -trigger1 = trigger.Trigger(trig_width, [term1]) -recorder1 = recorder.Recorder(dat_width, record_size) - -migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1, csr) - -#============================================================================== -# T E S T M I G L A -#============================================================================== -dat_vcd = [] -recorder1.size(1024) - -term1.write(0x0100005A,0x0100005A) -sum_tt = gen_truth_table("term1") -migLa1.trig.sum.write(sum_tt) -migLa1.rec.reset() -migLa1.rec.offset(256) -migLa1.rec.arm() - -print("-Recorder [Armed]") -print("-Waiting Trigger...", end = ' ') -csr.write(0x0000,0x5A) -while(not migLa1.rec.is_done()): - time.sleep(0.1) -print("[Done]") - -print("-Receiving Data...", end = ' ') -sys.stdout.flush() -dat_vcd += migLa1.rec.read(1024) -print("[Done]") - -myvcd = Vcd() -myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8))) -myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24))) -myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24))) -myvcd.write("test_MigLa_1.vcd") \ No newline at end of file diff --git a/examples/de1/client/test_MiIo.py b/examples/de1/client/test_MiIo.py new file mode 100644 index 00000000..338e09f2 --- /dev/null +++ b/examples/de1/client/test_MiIo.py @@ -0,0 +1,62 @@ +from migScope import trigger, recorder, migIo + +import sys +sys.path.append("../../../") + +from spi2Csr.tools.uart2Spi import * + +#============================================================================== +# P A R A M E T E R S +#============================================================================== +# Bus Width +trig_width = 16 +dat_width = 16 + +# Record Size +record_size = 1024 + +csr = Uart2Spi(1,115200) + +# Csr Addr +MIIO_ADDR = 0x0000 + +# Miscope Configuration +# miIo +miIo0 = miIo.MiIo(MIIO_ADDR, 8, "IO", csr) + +def led_anim0(): + for i in range(10): + miIo0.write(0xA5) + time.sleep(0.1) + miIo0.write(0x5A) + time.sleep(0.1) + +def led_anim1(): + #Led << + for j in range(4): + ledData = 1 + for i in range(8): + miIo0.write(ledData) + time.sleep(i*i*0.0020) + ledData = (ledData<<1) + #Led >> + ledData = 128 + for i in range(8): + miIo0.write(ledData) + time.sleep(i*i*0.0020) + ledData = (ledData>>1) + +#============================================================================== +# T E S T M I G I O +#============================================================================== + +print("- Small Led Animation...") +led_anim0() +time.sleep(1) +led_anim1() +time.sleep(1) + +print("- Read Switch: ",end=' ') +print(miIo0.read()) + + diff --git a/examples/de1/client/test_MiLa_0.py b/examples/de1/client/test_MiLa_0.py new file mode 100644 index 00000000..d687eae8 --- /dev/null +++ b/examples/de1/client/test_MiLa_0.py @@ -0,0 +1,83 @@ +from miscope import trigger, recorder, miIo, miLa +from miscope.tools.truthtable import * +from miscope.tools.vcd import * + +import sys +sys.path.append("../../../") + +from spi2Csr.tools.uart2Spi import * + +#============================================================================== +# P A R A M E T E R S +#============================================================================== +# Bus Width +trig_width = 16 +dat_width = 16 + +# Record Size +record_size = 4096 + +# Csr Addr +MIIO_ADDR = 0x0000 +MILA_ADDR = 0x0200 + +csr = Uart2Spi(1, 115200, debug=False) + +# MiScope Configuration +# miIo0 +miIo0 = miIo.MigIo(MIIO_ADDR, 8, "IO",csr) + +# miLa0 +term0 = trigger.Term(trig_width) +trigger0 = trigger.Trigger(trig_width, [term0]) +recorder0 = recorder.Recorder(dat_width, record_size) + +miLa0 = miLa.MiLa(MILA_ADDR, trigger0, recorder0, csr) + +#============================================================================== +# T E S T M I G L A +#============================================================================== +dat_vcd = [] +recorder0.size(1024) + +def capture(size): + global trigger0 + global recorder0 + global dat_vcd + sum_tt = gen_truth_table("term0") + miLa0.trig.sum.write(sum_tt) + miLa0.rec.reset() + miLa0.rec.offset(0) + miLa0.rec.arm() + print("-Recorder [Armed]") + print("-Waiting Trigger...", end = ' ') + while(not miLa0.rec.is_done()): + time.sleep(0.1) + print("[Done]") + + print("-Receiving Data...", end = ' ') + sys.stdout.flush() + dat_vcd += miLa0.rec.read(size) + print("[Done]") + +print("Capturing Ramp..") +print("----------------------") +term0.write(0x0000,0xFFFF) +csr.write(0x0000, 0) +capture(1024) + +print("Capturing Square..") +print("----------------------") +term0.write(0x0000,0xFFFF) +csr.write(0x0000, 1) +capture(1024) + +print("Capturing Sinus..") +print("----------------------") +term0.write(0x0080,0xFFFF) +csr.write(0x0000, 2) +capture(1024) + +myvcd = Vcd() +myvcd.add(Var("wire", 16, "trig_dat", dat_vcd)) +myvcd.write("test_MiLa_0.vcd") \ No newline at end of file diff --git a/examples/de1/client/test_MiLa_1.py b/examples/de1/client/test_MiLa_1.py new file mode 100644 index 00000000..d5c2beba --- /dev/null +++ b/examples/de1/client/test_MiLa_1.py @@ -0,0 +1,66 @@ +from miscope import trigger, recorder, miIo, miLa +from miscope.tools.truthtable import * +from miscope.tools.vcd import * + +import sys +sys.path.append("../../../") + +from spi2Csr.tools.uart2Spi import * + +#============================================================================== +# P A R A M E T E R S +#============================================================================== +# Bus Width +trig_width = 32 +dat_width = 32 + +# Record Size +record_size = 4096 + +# Csr Addr +MIIO0_ADDR = 0x0000 +MILA1_ADDR = 0x0600 + +csr = Uart2Spi(1, 115200, debug=False) + +# MiScope Configuration +# miIo0 +miIo0 = miIo.MigIo(MIIO0_ADDR, 8, "IO",csr) + +# miLa1 +term1 = trigger.Term(trig_width) +trigger1 = trigger.Trigger(trig_width, [term1]) +recorder1 = recorder.Recorder(dat_width, record_size) + +miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1, csr) + +#============================================================================== +# T E S T M I G L A +#============================================================================== +dat_vcd = [] +recorder1.size(1024) + +term1.write(0x0100005A,0x0100005A) +sum_tt = gen_truth_table("term1") +miLa1.trig.sum.write(sum_tt) +miLa1.rec.reset() +miLa1.rec.offset(256) +miLa1.rec.arm() + +print("-Recorder [Armed]") +print("-Waiting Trigger...", end = ' ') +csr.write(0x0000,0x5A) +while(not miLa1.rec.is_done()): + time.sleep(0.1) +print("[Done]") + +print("-Receiving Data...", end = ' ') +sys.stdout.flush() +dat_vcd += miLa1.rec.read(1024) +print("[Done]") + +myvcd = Vcd() +myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8))) +myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24))) +myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24))) +myvcd.write("test_MiLa_1.vcd") \ No newline at end of file diff --git a/examples/de1/client/test_MigIo.py b/examples/de1/client/test_MigIo.py deleted file mode 100644 index 64c8727c..00000000 --- a/examples/de1/client/test_MigIo.py +++ /dev/null @@ -1,69 +0,0 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * - -import sys -sys.path.append("../../../") - -from migScope import trigger, recorder, migIo -import spi2Csr -from spi2Csr.tools.uart2Spi import * - -#============================================================================== -# P A R A M E T E R S -#============================================================================== -# Bus Width -trig_width = 16 -dat_width = 16 - -# Record Size -record_size = 1024 - -csr = Uart2Spi(1,115200) - -# Csr Addr -MIGIO_ADDR = 0x0000 - -# MigScope Configuration -# migIo -migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr) - -def led_anim0(): - for i in range(10): - migIo0.write(0xA5) - time.sleep(0.1) - migIo0.write(0x5A) - time.sleep(0.1) - -def led_anim1(): - #Led << - for j in range(4): - ledData = 1 - for i in range(8): - migIo0.write(ledData) - time.sleep(i*i*0.0020) - ledData = (ledData<<1) - #Led >> - ledData = 128 - for i in range(8): - migIo0.write(ledData) - time.sleep(i*i*0.0020) - ledData = (ledData>>1) - -#============================================================================== -# T E S T M I G I O -#============================================================================== - -print("- Small Led Animation...") -led_anim0() -time.sleep(1) -led_anim1() -time.sleep(1) - -print("- Read Switch: ",end=' ') -print(migIo0.read()) - - diff --git a/examples/de1/client/test_MigLa_0.py b/examples/de1/client/test_MigLa_0.py deleted file mode 100644 index df8fd7f9..00000000 --- a/examples/de1/client/test_MigLa_0.py +++ /dev/null @@ -1,90 +0,0 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * - -import sys -sys.path.append("../../../") - -from migScope import trigger, recorder, migIo, migLa -from migScope.tools.truthtable import * -from migScope.tools.vcd import * -import spi2Csr -from spi2Csr.tools.uart2Spi import * - -#============================================================================== -# P A R A M E T E R S -#============================================================================== -# Bus Width -trig_width = 16 -dat_width = 16 - -# Record Size -record_size = 4096 - -# Csr Addr -MIGIO_ADDR = 0x0000 -MIGLA_ADDR = 0x0200 - -csr = Uart2Spi(1,115200,debug=False) - -# MigScope Configuration -# migIo0 -migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr) - -# migIla0 -term0 = trigger.Term(trig_width) -trigger0 = trigger.Trigger(trig_width, [term0]) -recorder0 = recorder.Recorder(dat_width, record_size) - -migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr) - -#============================================================================== -# T E S T M I G L A -#============================================================================== -dat_vcd = [] -recorder0.size(1024) - -def capture(size): - global trigger0 - global recorder0 - global dat_vcd - sum_tt = gen_truth_table("term0") - migLa0.trig.sum.write(sum_tt) - migLa0.rec.reset() - migLa0.rec.offset(0) - migLa0.rec.arm() - print("-Recorder [Armed]") - print("-Waiting Trigger...", end = ' ') - while(not migLa0.rec.is_done()): - time.sleep(0.1) - print("[Done]") - - print("-Receiving Data...", end = ' ') - sys.stdout.flush() - dat_vcd += migLa0.rec.read(size) - print("[Done]") - -print("Capturing Ramp..") -print("----------------------") -term0.write(0x0000,0xFFFF) -csr.write(0x0000, 0) -capture(1024) - -print("Capturing Square..") -print("----------------------") -term0.write(0x0000,0xFFFF) -csr.write(0x0000, 1) -capture(1024) - -print("Capturing Sinus..") -print("----------------------") -term0.write(0x0080,0xFFFF) -csr.write(0x0000, 2) -capture(1024) - -myvcd = Vcd() -myvcd.add(Var("wire", 16, "trig_dat", dat_vcd)) -myvcd.write("test_MigLa_0.vcd") \ No newline at end of file diff --git a/examples/de1/client/test_MigLa_1.py b/examples/de1/client/test_MigLa_1.py deleted file mode 100644 index 69c8e203..00000000 --- a/examples/de1/client/test_MigLa_1.py +++ /dev/null @@ -1,73 +0,0 @@ -from migen.fhdl.structure import * -from migen.fhdl import verilog, autofragment -from migen.bus import csr -from migen.bus.transactions import * -from migen.bank import description, csrgen -from migen.bank.description import * - -import sys -sys.path.append("../../../") - -from migScope import trigger, recorder, migIo, migLa -from migScope.tools.truthtable import * -from migScope.tools.vcd import * -import spi2Csr -from spi2Csr.tools.uart2Spi import * - -#============================================================================== -# P A R A M E T E R S -#============================================================================== -# Bus Width -trig_width = 32 -dat_width = 32 - -# Record Size -record_size = 4096 - -# Csr Addr -MIGIO0_ADDR = 0x0000 -MIGLA1_ADDR = 0x0600 - -csr = Uart2Spi(1,115200,debug=False) - -# MigScope Configuration -# migIo0 -migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr) - -# migIla1 -term1 = trigger.Term(trig_width) -trigger1 = trigger.Trigger(trig_width, [term1]) -recorder1 = recorder.Recorder(dat_width, record_size) - -migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1, csr) - -#============================================================================== -# T E S T M I G L A -#============================================================================== -dat_vcd = [] -recorder1.size(1024) - -term1.write(0x0100005A,0x0100005A) -sum_tt = gen_truth_table("term1") -migLa1.trig.sum.write(sum_tt) -migLa1.rec.reset() -migLa1.rec.offset(256) -migLa1.rec.arm() - -print("-Recorder [Armed]") -print("-Waiting Trigger...", end = ' ') -csr.write(0x0000,0x5A) -while(not migLa1.rec.is_done()): - time.sleep(0.1) -print("[Done]") - -print("-Receiving Data...", end = ' ') -sys.stdout.flush() -dat_vcd += migLa1.rec.read(1024) -print("[Done]") - -myvcd = Vcd() -myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8))) -myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24))) -myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24))) -myvcd.write("test_MigLa_1.vcd") \ No newline at end of file