From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Wed, 18 Mar 2020 21:23:43 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f827ee65e99ba7b75d6d2d5bd0241162c7cf758e;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
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+Date: Wed, 18 Mar 2020 21:23:43 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Specification
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
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+Message-ID: <bug-186-13-ETBowT7GmJ@http.bugs.libre-riscv.org/>
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+References: <bug-186-13@http.bugs.libre-riscv.org/>
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+Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
+ RISC-V
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