From: whitequark <whitequark@whitequark.org>
Date: Wed, 27 Nov 2019 17:58:42 +0000 (+0000)
Subject: back.rtlil: infer bit width for instance parameters.
X-Git-Tag: v0.2~49
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8428ff5051c2c7295e93a0a191880076b5dffab;p=nmigen.git

back.rtlil: infer bit width for instance parameters.

Otherwise, Yosys assumes it is always 32, which is often
inappropriate.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 7806ace..9869c61 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -128,8 +128,8 @@ class _ModuleBuilder(_Namer, _BufferedBuilder, _AttrBuilder):
                 self._append("    parameter \\{} \"{}\"\n",
                              param, value.translate(self._escape_map))
             elif isinstance(value, int):
-                self._append("    parameter \\{} {:d}\n",
-                             param, value)
+                self._append("    parameter \\{} {}'{:b}\n",
+                             param, bits_for(value), value)
             elif isinstance(value, float):
                 self._append("    parameter real \\{} \"{!r}\"\n",
                              param, value)