From: lkcl <lkcl@web>
Date: Sun, 24 Jan 2021 13:04:33 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~360
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f848df28891418aa967bb4a680ddb4e98ec13e16;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 651b3ae6c..8256443a5 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -302,7 +302,14 @@ permutations of vector selection, to identify above asm-syntax:
 
 TODO: indexed mode
 
-     RA,RB    RT.v  RA/RB.v ffirst banned
-     RA,RB    RT.s  RA/RB.v ffirst banned
-     RA,RB    RT.v  RA/RB.s VSPLAT possible
-     RA,RB    RT.s  RA/RB.s not vectorised
+     RA,RB    RT.v  RA.v  RB.v
+        sv.ldx r#.v, r#2, r#3.v -> whole vector at r#2+r#3
+     RA,RB    RT.v  RA.s  RB.v
+        sv.ldx r#.v, r#2.v, r#3.v -> whole vector at r#2+r#3
+     RA,RB    RT.v  RA.v  RB.s
+        sv.ldx r#.v, r#2.v, r#3 -> vector of addresses
+     RA,RB    RT.v  RA.s  RB.s
+     RA,RB    RT.s  RA.v  RB.v
+     RA,RB    RT.s  RA.s  RB.v
+     RA,RB    RT.s  RA.v  RB.s
+     RA,RB    RT.s  RA.s  RB.s not vectorised