From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Tue, 17 Mar 2015 11:35:24 +0000 (-0700)
Subject: relay hwacha cause/aux to scause/sbadaddr
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f84936393dccd1367d3cb2a1fa060e77eb7babec;p=riscv-tests.git

relay hwacha cause/aux to scause/sbadaddr
---

diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index b4d0d78..83116f2 100644
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -596,10 +596,10 @@ vtcode2 ## testnum: \
 handler ## testnum: \
   vxcptkill; \
   li TESTNUM,2; \
-  vxcptcause a0; \
+  csrr a0, scause; \
   li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
   bne a0,a1,fail; \
-  vxcptaux a0; \
+  csrr a0, sbadaddr; \
   la a1, illegal ## testnum; \
   lw a2, 0(a1); \
   bne a0, a2, fail; \
@@ -655,10 +655,10 @@ vtcode2 ## testnum: \
 handler ## testnum: \
   vxcptkill; \
   li TESTNUM,2; \
-  vxcptcause a0; \
+  csrr a0, scause; \
   li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
   bne a0,a1,fail; \
-  vxcptaux a0; \
+  csrr a0, sbadaddr; \
   la a1,illegal ## testnum; \
   bne a0,a1,fail; \
   vsetcfg 32,0; \
diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index a2c9827..03227eb 100644
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -30,12 +30,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_ILLEGAL_CFG
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   li a4, 1
   bne a3,a4,fail
 
diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index db07744..dc4d3a4 100644
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -29,12 +29,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_ILLEGAL_CFG
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   li a4, 0
   bne a3,a4,fail
 
diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index ae46fe0..b7dfc28 100644
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -36,12 +36,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_ILLEGAL_INSTRUCTION
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   li a4, 0xff00002b
   bne a3,a4,fail
 
diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index dd61697..e216413 100644
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -44,12 +44,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION
   bne a3,a4,fail
 
   # check badvaddr
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,illegal
   bne a3,a4,fail
 
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index 398396e..79b21b1 100644
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -40,12 +40,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_LOAD
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 
diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 1390b54..9bd3cd8 100644
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -42,12 +42,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_STORE
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4, dest+1
   bne a3,a4,fail
 
diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index 4276b64..85882b8 100644
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -41,12 +41,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_LOAD
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 
diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index 2271e8f..35cb828 100644
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -44,12 +44,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_STORE
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 
diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index 25c23c5..d7c96b3 100644
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -34,12 +34,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
   bne a3,a4,fail
 
   # check badvaddr
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,vtcode1+2
   andi a3, a3, -4 # mask off lower bits so that may
   andi a4, a4, -4 # ignore impl. specific behavior
diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index b7b169e..65c5288 100644
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -36,12 +36,12 @@ handler:
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4, privileged_inst
   lw a5, 0(a4)
   bne a3,a5,fail