From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun, 24 May 2020 11:57:02 +0000 (+0200)
Subject: radv: Disable DCC in ac_surface.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f84b4e2639246d23fe94b4688fd75e3d11662205;p=mesa.git

radv: Disable DCC in ac_surface.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5194>
---

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 064084cbe28..fdb8177abbc 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -149,6 +149,23 @@ radv_surface_has_scanout(struct radv_device *device, const struct radv_image_cre
 	return info->scanout;
 }
 
+static bool
+radv_image_use_fast_clear_for_image(const struct radv_image *image)
+{
+	if (image->info.samples <= 1 &&
+	    image->info.width * image->info.height <= 512 * 512) {
+		/* Do not enable CMASK or DCC for small surfaces where the cost
+		 * of the eliminate pass can be higher than the benefit of fast
+		 * clear. RadeonSI does this, but the image threshold is
+		 * different.
+		 */
+		return false;
+	}
+
+	return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
+	       (image->exclusive || image->queue_family_mask == 1);
+}
+
 static bool
 radv_use_dcc_for_image(struct radv_device *device,
 		       const struct radv_image *image,
@@ -179,6 +196,9 @@ radv_use_dcc_for_image(struct radv_device *device,
 	    vk_format_get_plane_count(format) > 1)
 		return false;
 
+	if (!radv_image_use_fast_clear_for_image(image))
+		return false;
+
 	/* TODO: Enable DCC for mipmaps on GFX9+. */
 	if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
 	    device->physical_device->rad_info.chip_class >= GFX9)
@@ -1267,33 +1287,6 @@ radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
 	image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
 }
 
-static inline bool
-radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
-{
-	if (image->info.samples <= 1 &&
-	    image->info.width * image->info.height <= 512 * 512) {
-		/* Do not enable CMASK or DCC for small surfaces where the cost
-		 * of the eliminate pass can be higher than the benefit of fast
-		 * clear. RadeonSI does this, but the image threshold is
-		 * different.
-		 */
-		return false;
-	}
-
-	return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
-	       (image->exclusive || image->queue_family_mask == 1);
-}
-
-static inline bool
-radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
-{
-	if (!radv_image_can_enable_dcc_or_cmask(image) ||
-	    !radv_image_has_dcc(image))
-		return false;
-
-	return true;
-}
-
 static inline bool
 radv_image_can_enable_cmask(struct radv_image *image)
 {
@@ -1305,7 +1298,7 @@ radv_image_can_enable_cmask(struct radv_image *image)
 		return false;
 	}
 
-	return radv_image_can_enable_dcc_or_cmask(image) &&
+	return radv_image_use_fast_clear_for_image(image) &&
 	       image->info.levels == 1 &&
 	       image->info.depth == 1;
 }
@@ -1377,7 +1370,7 @@ radv_image_create_layout(struct radv_device *device,
 	}
 
 	/* Try to enable DCC first. */
-	if (radv_image_can_enable_dcc(device, image)) {
+	if (radv_image_has_dcc(image)) {
 		radv_image_alloc_dcc(image);
 		if (image->info.samples > 1) {
 			/* CMASK should be enabled because DCC fast