From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Mon, 20 Dec 2021 16:10:30 +0000 (+0100)
Subject: memory_share: Fix SAT-based sharing for wide ports.
X-Git-Tag: yosys-0.13~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f84c9d8e17fbbfa3c0f8b533475e10142e046556;p=yosys.git

memory_share: Fix SAT-based sharing for wide ports.

Fixes #3117.
---

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 9d82739aa..ceea725d8 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -416,7 +416,9 @@ struct MemoryShareWorker
 					else
 						this_addr.extend_u0(GetSize(last_addr));
 
-					port1.addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
+					SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active);
+
+					port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)});
 					port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
 
 					std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
diff --git a/tests/opt/bug3117.ys b/tests/opt/bug3117.ys
new file mode 100644
index 000000000..177b3ab9a
--- /dev/null
+++ b/tests/opt/bug3117.ys
@@ -0,0 +1,34 @@
+read_verilog << EOT
+
+module test (...);
+
+input [7:1] wa1;
+input [7:1] wa2;
+input [7:0] ra;
+output [7:0] rd;
+input clk;
+input we1, we2;
+input [15:0] wd1, wd2;
+
+reg [7:0] mem [0:255];
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+        if (we1) begin
+                mem[{wa1, 1'b0}] <= wd1[7:0];
+                mem[{wa1, 1'b1}] <= wd1[15:8];
+        end else begin
+                mem[{wa2, 1'b0}] <= wd2[7:0];
+                mem[{wa2, 1'b1}] <= wd2[15:8];
+        end
+end
+
+endmodule
+
+EOT
+
+proc
+opt
+memory_share
+select -assert-count 1 t:$memwr_v2