From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 04:09:40 +0000 (-0800)
Subject: abc9 to write_aiger with -O option, and ignore dummy outputs
X-Git-Tag: working-ls180~1237^2~315
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f853b2f3c15f629ea22a9427e5524bdeebddfb8f;p=yosys.git

abc9 to write_aiger with -O option, and ignore dummy outputs
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2cc79fa95..f684ad8de 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -412,8 +412,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 	handle_loops(design, module);
 
     Pass::call(design, "write_verilog -norename -noexpr input.v");
-    Pass::call(design, stringf("write_xaiger -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
-    Pass::call(design, stringf("write_xaiger -ascii -symbols %s/input.xaag; read_aiger -wideports -map %s/input.symbols %s/input.xaag; write_verilog -norename -noexpr input.v", tempdir_name.c_str(), tempdir_name.c_str(), tempdir_name.c_str()));
+    Pass::call(design, stringf("write_xaiger -O -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
+    Pass::call(design, stringf("write_xaiger -ascii -symbols %s/input.xaag; read_aiger -wideports %s/input.xaag; write_verilog -norename -noexpr input.v", tempdir_name.c_str(), tempdir_name.c_str()));
 
 	// Now 'unexpose' those wires by undoing
 	// the expose operation -- remove them from PO/PI
@@ -547,6 +547,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 						output_bits.insert({wire, i});
 				}
 				else {
+					if (w->name.str() == "\\__dummy_o__") {
+						log("Don't call ABC as there is nothing to map.\n");
+						goto cleanup;
+					}
+
 					auto r = wideports_split(w->name.str());
 					wire = module->wire(r.first);
 					log_assert(wire);
@@ -875,6 +880,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
 	Pass::call(design, "clean");
 
+cleanup:
 	if (cleanup)
 	{
 		log("Removing temp directory.\n");