From: Jim Blandy <jimb@codesourcery.com>
Date: Thu, 15 Jul 2004 08:02:36 +0000 (+0000)
Subject: * ppc-tdep.h (struct gdbarch_tdep): New member: ppc_sr0_regnum.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f86a7158a9911e23363c4820ac47f757e92c3963;p=binutils-gdb.git

* ppc-tdep.h (struct gdbarch_tdep): New member: ppc_sr0_regnum.
* rs6000-tdep.c (rs6000_gdbarch_init): Initialize it.
---

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index ef79365aa83..eab68155b24 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2004-07-15  Jim Blandy  <jimb@redhat.com>
+
+	* ppc-tdep.h (struct gdbarch_tdep): New member: ppc_sr0_regnum.
+	* rs6000-tdep.c (rs6000_gdbarch_init): Initialize it.
+
 2004-07-14  Jim Blandy  <jimb@redhat.com>
 
 	* rs6000-tdep.c (COMMON_UISA_NOFP_REGS): Delete; unused.
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index ac08c617583..a64579253b5 100644
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -158,6 +158,10 @@ struct gdbarch_tdep
     int ppc_fpscr_regnum;	/* Floating point status and condition
     				   register */
 
+    int ppc_sr0_regnum;         /* segment register 0, or -1 on
+                                   variants that have no segment
+                                   registers.  */
+
     int ppc_mq_regnum;		/* Multiply/Divide extension register */
     int ppc_vr0_regnum;		/* First AltiVec register */
     int ppc_vrsave_regnum;	/* Last AltiVec register */
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index e3bde46d7fc..3676b856f46 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -2868,6 +2868,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
     tdep->ppc_mq_regnum = -1;
   tdep->ppc_fp0_regnum = 32;
   tdep->ppc_fpscr_regnum = power ? 71 : 70;
+  tdep->ppc_sr0_regnum = 71;
   tdep->ppc_vr0_regnum = -1;
   tdep->ppc_vrsave_regnum = -1;
   tdep->ppc_ev0_regnum = -1;
@@ -2896,7 +2897,9 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   else
     tdep->lr_frame_offset = 8;
 
-  if (v->arch == bfd_arch_powerpc)
+  if (v->arch == bfd_arch_rs6000)
+    tdep->ppc_sr0_regnum = -1;
+  else if (v->arch == bfd_arch_powerpc)
     switch (v->mach)
       {
       case bfd_mach_ppc: 
@@ -2920,6 +2923,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 	tdep->ppc_ev31_regnum = 38;
         tdep->ppc_fp0_regnum = -1;
         tdep->ppc_fpscr_regnum = -1;
+        tdep->ppc_sr0_regnum = -1;
         tdep->ppc_acc_regnum = 39;
         tdep->ppc_spefscr_regnum = 40;
         set_gdbarch_pc_regnum (gdbarch, 0);
@@ -2928,7 +2932,21 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
         set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
         set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
 	break;
+
+      case bfd_mach_ppc64:
+      case bfd_mach_ppc_620:
+      case bfd_mach_ppc_630:
+      case bfd_mach_ppc_a35:
+      case bfd_mach_ppc_rs64ii:
+      case bfd_mach_ppc_rs64iii:
+        /* These processor's register sets don't have segment registers.  */
+        tdep->ppc_sr0_regnum = -1;
+        break;
       }   
+  else
+    internal_error (__FILE__, __LINE__,
+                    "rs6000_gdbarch_init: "
+                    "received unexpected BFD 'arch' value");
 
   /* Sanity check on registers.  */
   gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);