From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 8 Mar 2020 12:33:34 +0000 (+0000)
Subject: start adding DecodeA
X-Git-Tag: div_pipeline~1761
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f875c40bc8833c93e4e93ee28e7164f6deaab948;p=soc.git

start adding DecodeA
---

diff --git a/src/decoder/power_decoder2.py b/src/decoder/power_decoder2.py
index 0a19d303..f3c7dded 100644
--- a/src/decoder/power_decoder2.py
+++ b/src/decoder/power_decoder2.py
@@ -4,7 +4,37 @@ based on Anton Blanchard microwatt decode2.vhdl
 
 """
 from nmigen import Module, Elaboratable, Signal
-from power_enums import InternalOp, CryIn
+from power_enums import (InternalOp, CryIn,
+                         In1Sel, In2Sel, In3Sel, OutSel)
+
+class DecodeA(Elaboratable):
+    def __init__(self, dec):
+        self.dec = dec
+        self.sel_in = Signal(In1Sel, reset_less=True)
+        self.insn_in = Signal(32, reset_less=True)
+        self.ispr1_in = Signal(10, reset_less=True)
+        self.reg_out = Signal(5, reset_less=True)
+        self.regok_out = Signal(reset_less=True)
+        self.spr_out = Signal(10, reset_less=True)
+        self.sprok_out = Signal(reset_less=True)
+
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+
+        # select Register A field
+        comb += self.reg_out.eq(self.dec.RA)
+        with m.If((self.sel_in == In1Sel.RA) |
+                  ((self.sel_in == In1Sel.RA_OR_ZERO) & (ra == Const(0, 5))):
+            comb += self.regok_out.eq(1)
+
+        # decode SPR1 based on instruction type
+        op = self.dec.op
+        with m.If(op.internal_op == InternalOP.OP_BC |
+                  op.internal_op == InternalOP.OP_BCREG):
+            with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
+                self.spr_out.eq(SPR_CTR)
+                self.sprok_out.eq(1)
 
 
 class XerBits: