From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 8 Feb 2015 23:18:36 +0000 (+0100)
Subject: Fixed iterator invalidation bug in "rename" command
X-Git-Tag: yosys-0.5~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f889e3d38524bb3cb6a10ccd33f788e987c6e14e;p=yosys.git

Fixed iterator invalidation bug in "rename" command
---

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 8f24af278..17d803e96 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -34,9 +34,10 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 
 	for (auto &it : module->wires_)
 		if (it.first == from_name) {
-			log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
-			module->rename(it.second, to_name);
-			if (it.second->port_id)
+			Wire *w = it.second;
+			log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module));
+			module->rename(w, to_name);
+			if (w->port_id)
 				module->fixup_ports();
 			return;
 		}