From: Gabe Black <gabeblack@google.com>
Date: Wed, 11 Sep 2019 20:45:24 +0000 (-0700)
Subject: x86: Switch from MessageReq and Resp to WriteReq and Resp.
X-Git-Tag: v19.0.0.0~488
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f89f85d255e2192fa2aab5dd168eb9372c41d09c;p=gem5.git

x86: Switch from MessageReq and Resp to WriteReq and Resp.

Originally MessageReq was intended to mark a packet as a holding a
message destined for a particular recipient and which would not
interact with other packets.

This is similar to the way a WriteReq would behave if writing to a
device register which needs to be updated atomically. Also, while the
memory system *could* recognize a MessageReq and know that it didn't
need to interact with other packets, that was never implemented.

Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
---

diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 402b91200..392135def 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -307,7 +307,7 @@ Tick
 X86ISA::Interrupts::recvMessage(PacketPtr pkt)
 {
     Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
-    assert(pkt->cmd == MemCmd::MessageReq);
+    assert(pkt->cmd == MemCmd::WriteReq);
     switch(offset)
     {
       case 0:
@@ -335,7 +335,7 @@ bool
 X86ISA::Interrupts::recvResponse(PacketPtr pkt)
 {
     assert(!pkt->isError());
-    assert(pkt->cmd == MemCmd::MessageResp);
+    assert(pkt->cmd == MemCmd::WriteResp);
     if (--pendingIPIs == 0) {
         InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
         // Record that the ICR is now idle.
diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh
index 8ec60b2aa..429b0f9f6 100644
--- a/src/arch/x86/intmessage.hh
+++ b/src/arch/x86/intmessage.hh
@@ -84,7 +84,7 @@ namespace X86ISA
             size, Request::UNCACHEABLE,
             Request::intMasterId);
 
-        PacketPtr pkt = new Packet(req, MemCmd::MessageReq);
+        PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
         pkt->allocate();
         return pkt;
     }
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index f71c9ff9d..348ec57b8 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -76,7 +76,7 @@ class IntSlavePort : public SimpleTimingPort
     Tick
     recvAtomic(PacketPtr pkt)
     {
-        panic_if(pkt->cmd != MemCmd::MessageReq,
+        panic_if(pkt->cmd != MemCmd::WriteReq,
                 "%s received unexpected command %s from %s.\n",
                 name(), pkt->cmd.toString(), getPeer());
         pkt->headerDelay = pkt->payloadDelay = 0;