From: Clifford Wolf Date: Sat, 26 Jul 2014 09:23:43 +0000 (+0200) Subject: Added "Checklist for adding internal cell types" X-Git-Tag: yosys-0.4~426 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8a68b8f55ed61c6046e11b60587c840f0ba1879;p=yosys.git Added "Checklist for adding internal cell types" --- diff --git a/CHECKLIST b/CHECKLIST deleted file mode 100644 index 35de389be..000000000 --- a/CHECKLIST +++ /dev/null @@ -1,108 +0,0 @@ - - -Checklist for creating Yosys releases -===================================== - - -Update the CHANGELOG file: - - cd ~yosys - gitk & - vi CHANGELOG - - -Run all tests with "make config-{clang-debug,gcc-debug,gcc-4.7,release}": - - cd ~yosys - make clean - make test vloghtb - make install - - cd ~yosys-bigsim - make clean - make full - - cd ~vloghammer - make purge - make gen_issues gen_samples - make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" FULL=1 world - chromium-browser report.html - - -Then with default config setting: - - cd ~yosys - ./yosys -p 'proc; show' tests/simple/fiedler-cooley.v - ./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v - - cd ~yosys - make manual - - sanity check the figures in the appnotes and presentation - - if there are any odd things -> investigate - - make cosmetic changes to the .tex files if necessary - - -Also with default config setting: - - cd ~yosys/techlibs/cmos - bash testbench.sh - - cd ~yosys/techlibs/xilinx/example_sim_counter - bash run_sim.sh - - cd ~yosys/techlibs/xilinx/example_mojo_counter - bash example.sh - - -Finally if a current verific library is available: - - cd ~yosys - cat frontends/verific/build_amd64.txt - - follow instructions - - cd frontends/verific - ../../yosys test_navre.ys - - -Release candiate: - - - create branch yosys-x.y.z-rc and push to github - - contact the usual suspects per mail and ask them to test - - post on the reddit and ask people to test - - commit KISS fixes to the -rc branch if necessary - - -Release: - - - set YOSYS_VER to x.y.z in Makefile - - update version string in CHANGELOG - git commit -am "Yosys x.y.z" - - - push tag to github - - post changelog on github - - post short release note on reddit - - delete -rc branch from github - - -Updating the website: - - cd ~yosys - make manual - make install - - - update pdf files on the website - - cd ~yosys-web - make update_cmd - make update_show - git commit -am update - make push - - -In master branch: - - git merge {release-tag} - - set version to x.y.z+ in Makefile - - add section "Yosys x.y.z .. x.y.z+" to CHANGELOG - git commit --amend -am "Yosys x.y.z+" - diff --git a/CHECKLISTS b/CHECKLISTS new file mode 100644 index 000000000..3f824fc28 --- /dev/null +++ b/CHECKLISTS @@ -0,0 +1,132 @@ + +This file contains checklists for various tasks. + + +Table of contents +================= + +1. Checklist for creating Yosys releases +2. Checklist for adding internal cell types + + +1. Checklist for creating Yosys releases +======================================== + + +Update the CHANGELOG file: + + cd ~yosys + gitk & + vi CHANGELOG + + +Run all tests with "make config-{clang-debug,gcc-debug,gcc-4.7,release}": + + cd ~yosys + make clean + make test vloghtb + make install + + cd ~yosys-bigsim + make clean + make full + + cd ~vloghammer + make purge + make gen_issues gen_samples + make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" FULL=1 world + chromium-browser report.html + + +Then with default config setting: + + cd ~yosys + ./yosys -p 'proc; show' tests/simple/fiedler-cooley.v + ./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v + + cd ~yosys + make manual + - sanity check the figures in the appnotes and presentation + - if there are any odd things -> investigate + - make cosmetic changes to the .tex files if necessary + + +Also with default config setting: + + cd ~yosys/techlibs/cmos + bash testbench.sh + + cd ~yosys/techlibs/xilinx/example_sim_counter + bash run_sim.sh + + cd ~yosys/techlibs/xilinx/example_mojo_counter + bash example.sh + + +Finally if a current verific library is available: + + cd ~yosys + cat frontends/verific/build_amd64.txt + - follow instructions + + cd frontends/verific + ../../yosys test_navre.ys + + +Release candiate: + + - create branch yosys-x.y.z-rc and push to github + - contact the usual suspects per mail and ask them to test + - post on the reddit and ask people to test + - commit KISS fixes to the -rc branch if necessary + + +Release: + + - set YOSYS_VER to x.y.z in Makefile + - update version string in CHANGELOG + git commit -am "Yosys x.y.z" + + - push tag to github + - post changelog on github + - post short release note on reddit + - delete -rc branch from github + + +Updating the website: + + cd ~yosys + make manual + make install + + - update pdf files on the website + + cd ~yosys-web + make update_cmd + make update_show + git commit -am update + make push + + +In master branch: + + git merge {release-tag} + - set version to x.y.z+ in Makefile + - add section "Yosys x.y.z .. x.y.z+" to CHANGELOG + git commit --amend -am "Yosys x.y.z+" + + +2. Checklist for adding internal cell types +=========================================== + +Things to do right away: + + - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells) + - Add to InternalCellChecker::check() in kernel/rtlil.cc + +Things to do after finalizing the cell interface: + + - Add support to kernel/satgen.h for the new cell type + - Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom) + - Maybe add support to the verilog backend for dumping such cells as expression +