From: Arnaud Durand Date: Thu, 19 Dec 2019 07:53:44 +0000 (+0100) Subject: Revert "gen/fhdl/verilog: allow single element verilog inline attribute" X-Git-Tag: 24jan2021_ls180~792^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8c58216580e223558b539fa3f9a0a6969bdf9a3;p=litex.git Revert "gen/fhdl/verilog: allow single element verilog inline attribute" This reverts commit b845755995a8517d8e0ffa86156fb5577201f7d4. --- diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py index dc3c5146..3e192d93 100644 --- a/litex/build/lattice/diamond.py +++ b/litex/build/lattice/diamond.py @@ -10,6 +10,8 @@ import shutil from migen.fhdl.structure import _Fragment +from litex.gen.fhdl.verilog import DummyAttrTranslate + from litex.build.generic_platform import * from litex.build import tools from litex.build.lattice import common diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index b0fc69fa..0e34af26 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -198,13 +198,11 @@ def _printattr(attr, attr_translate): firsta = True for attr in sorted(attr, key=lambda x: ("", x) if isinstance(x, str) else x): - # platform-dependent attribute if isinstance(attr, tuple): + # platform-dependent attribute attr_name, attr_value = attr - elif attr not in attr_translate.keys(): - attr_name, attr_value = attr, None - # translated attribute else: + # translated attribute at = attr_translate[attr] if at is None: continue @@ -212,9 +210,7 @@ def _printattr(attr, attr_translate): if not firsta: r += ", " firsta = False - r += attr_name - if attr_value is not None: - r += " = \"" + attr_value + "\"" + r += attr_name + " = \"" + attr_value + "\"" if r: r = "(* " + r + " *)" return r @@ -370,9 +366,14 @@ def _printspecials(overrides, specials, ns, add_data_file, attr_translate): return r +class DummyAttrTranslate: + def __getitem__(self, k): + return (k, "true") + + def convert(f, ios=None, name="top", special_overrides=dict(), - attr_translate={}, + attr_translate=DummyAttrTranslate(), create_clock_domains=True, display_run=False, reg_initialization=True,