From: Luis Machado Date: Sat, 16 May 2020 02:06:52 +0000 (-0300) Subject: Fix PR 26000, logical bitwise error / prologue analyzer X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8c6d1528c19b11fdaa3ec949147280e500446e2;p=binutils-gdb.git Fix PR 26000, logical bitwise error / prologue analyzer This fixes an instruction mask typo. We should be matching only ldrd (immediate) and not any other of its variants. As is, it never matches anything. With the patch, the instruction mask also allows matching of ldrd (literal), but the check for SP discards this particular instruction pattern, as it has a hardcoded PC register. gdb/ChangeLog: 2020-05-27 Luis Machado PR tdep/26000 * arm-tdep.c (thumb_analyze_prologue): Fix instruction matching for ldrd (immediate). --- diff --git a/gdb/ChangeLog b/gdb/ChangeLog index b0ec14fd4f9..6cadd332324 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,9 @@ +2020-05-27 Luis Machado + + PR tdep/26000 + * arm-tdep.c (thumb_analyze_prologue): Fix instruction matching + for ldrd (immediate). + 2020-05-26 Philippe Waroquiers * command.h: Add comment giving the name of class_tui. diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 3e085245c8e..5c5efe52e6e 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -931,7 +931,7 @@ thumb_analyze_prologue (struct gdbarch *gdbarch, parameters from memory. */ ; - else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2, + else if ((insn & 0xff70) == 0xe950 /* ldrd Rt, Rt2, [Rn, #+/-imm] */ && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) /* Similarly ignore dual loads from the stack. */