From: lkcl Date: Thu, 11 May 2023 16:23:22 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8cc21c7d086c90e6ec241a169b6aeceb208fbb9;p=libreriscv.git --- diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index e0c0a9ee0..46e9578be 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -551,9 +551,11 @@ sequentially through these registers (LSB0 sequential ordering from 0 to VL-1). Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is -r0 to r31, SV extends this as r0 to r127. Likewise FP registers are +r0 to r31, SV extends this range (in the Upper Compliancy Levels of SV) +as r0 to r127. Likewise FP registers are extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries, -CR0 thru CR127. +CR0 thru CR127. In the Lower SV Compliancy Levels the quantity of regiaters +remains the same in order to reduce implementation cost for Embedded systems. The names of the registers therefore reflects a simple linear extension of the Power ISA v3.0B / v3.1B register naming, and in hardware this