From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 15 Feb 2019 23:23:26 +0000 (-0800)
Subject: Move lookup inside if
X-Git-Tag: working-ls180~1237^2~325
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8d01345980a212a340087b6d9c0a8992f5b169c;p=yosys.git

Move lookup inside if
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index b32facc48..492911177 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -455,9 +455,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
 			if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx;
 			design->select(module, remap_wire);
-			RTLIL::Wire *wire = module->wire(w->name);
 			if (w->port_output) {
-				for (int i = 0; i < GetSize(remap_wire); i++)
+				RTLIL::Wire *wire = module->wire(w->name);
+				for (int i = 0; i < GetSize(wire); i++)
 					output_bits.insert({wire, i});
 			}
 		}