From: lkcl <lkcl@web>
Date: Mon, 21 Dec 2020 04:58:45 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1096
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8d7d38b876d9f1f45384d236500e7b7a41754e0;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 73a1904fc..f7af5b19a 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -131,6 +131,7 @@ is based on whether the number of src operands is 2 or 3.
 | Rdest\_EXTRA3 | `8:10`  | extends Rdest (Uses R\*\_EXTRA3 Encoding) |
 | Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1 (Uses R\*\_EXTRA3 Encoding) |
 | Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3 (Uses R\*\_EXTRA3 Encoding) |
+| ELWIDTH_SRC   | `17:18` | Element Width for Source      |
 | MODE          | `19:23` | changes Vector behaviour                  |
 
 These are for 2 operand 1 dest instructions, such as `add RT, RA,