From: Michael LeBeane <Michael.Lebeane@amd.com>
Date: Thu, 17 May 2018 21:17:24 +0000 (-0400)
Subject: arch-gcn3: Fix writelane src0,src1 usage
X-Git-Tag: v20.1.0.0~473
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8e295922b9b59c7157dbd79cd0bba734497ff3a;p=gem5.git

arch-gcn3: Fix writelane src0,src1 usage

Src1 should only be used for lane select.  The data should come
from src0.

Change-Id: Ibe960df2e56d351a3819b40194104d2972a5cd4c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29933
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
---

diff --git a/src/arch/gcn3/insts/instructions.cc b/src/arch/gcn3/insts/instructions.cc
index 0256d469b..b923eaeff 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -30181,7 +30181,7 @@ namespace Gcn3ISA
         assert(!(extData.NEG & 0x2));
         assert(!(extData.NEG & 0x4));
 
-        vdst[src1.rawData() & 0x3f] = src1.rawData();
+        vdst[src1.rawData() & 0x3f] = src0.rawData();
 
         vdst.write();
     }