From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Apr 2023 20:01:28 +0000 (+0100)
Subject: add implicit rs detection for maddsubrs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8e2c0cb1467391aa7ae4b8b092c281ee2e16a7b;p=openpower-isa.git

add implicit rs detection for maddsubrs
---

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 88b20238..2b9af402 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1066,6 +1066,12 @@ class PowerDecodeSubset(Elaboratable):
                 )):
                 comb += self.implicit_rs.eq(1)
                 comb += self.extend_rc_maxvl.eq(1) # RS=RT+MAXVL or RS=RC
+            # implicit RS for major 22, integer maddsubrs
+            with m.If((major == 22) & xo6.matches(
+                    '-01000',  # maddsubrs
+                )):
+                comb += self.implicit_rs.eq(1)
+                comb += self.extend_rb_maxvl.eq(1) # extend RB
 
         # rc and oe out
         comb += self.do_copy("rc", dec_rc.rc_out)