From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 01:56:50 +0000 (-0700)
Subject: Small opt
X-Git-Tag: working-ls180~881^2^2~274
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8f0ffe786eabd016e0f9a0e4f4de10743638cdf;p=yosys.git

Small opt
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 11c5e3570..b599160cf 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -749,7 +749,6 @@ void AigerReader::post_process()
 		log_assert(box_module);
 
 		RTLIL::Module* flop_module = nullptr;
-		const RTLIL::IdString flop_past_q = RTLIL::escape_id("\\$pastQ");
 		if (seen_boxes.insert(cell->type).second) {
 			auto it = box_module->attributes.find("\\abc_flop");
 			if (it != box_module->attributes.end()) {
@@ -830,7 +829,7 @@ void AigerReader::post_process()
 				rhs.append(wire);
 			}
 
-			if (!flop_module || port_name != flop_past_q)
+			if (!flop_module || port_name != "\\$pastQ")
 				cell->setPort(port_name, rhs);
 		}