From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 May 2018 16:44:41 +0000 (+0100)
Subject: more slides
X-Git-Tag: convert-csv-opcode-to-binary~5363
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8f2e0f9a4d43ce3bcb9dc9b23403c4adad5505d;p=libreriscv.git

more slides
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 3b0760744..4fe915a8f 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -1,10 +1,8 @@
-
 \documentclass[slidestop]{beamer}
 \usepackage{beamerthemesplit}
 \usepackage{graphics}
 \usepackage{pstricks}
 
-
 \title{Simple-V RISC-V Extension for Vectorisation and SIMD}
 \author{Luke Kenneth Casson Leighton}
 
@@ -85,6 +83,26 @@
   \end{itemize}
 }
 
+\begin{frame}[fragile]
+\frametitle{ADD pseudocode (or trap, or actual hardware loop)}
+
+\begin{semiverbatim}
+function op_add(rd, rs1, rs2, predr) \{
+  int i, id=0, irs1=0, irs2=0;
+  for (i=0; i < MIN(VL, vectorlen[rd]); i++)
+    if (predicate[predr][i]) # integer regfile: bitfield
+       x[rd+id] <= x[rs1+irs1] + x[rs2+irs2];
+    # now increment idxs: src/dest all vec/scalar
+    if (reg_is_vectorised[rd]) \{ id += 1; \}
+    if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}
+    if (reg_is_vectorised[rs2]) \{ irs2 += 1; \}
+\}
+\end{semiverbatim}
+   \begin{itemize}
+   \item Scalar-scalar and scalar-vector and vector-vector now all in one
+   \item OoO may choose to push ADDs into instr. queue (v. busy!)
+  \end{itemize}
+\end{frame}
 
 \frame{\frametitle{How are SIMD Instructions Vectorised?}