From: Gabriel Somlo <gsomlo@gmail.com>
Date: Wed, 9 Oct 2019 18:25:41 +0000 (-0400)
Subject: cpu/rocket: swap main_mem and io regions
X-Git-Tag: 24jan2021_ls180~932^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f8f643a02f8477d86bae11ddbcee442a88e835de;p=litex.git

cpu/rocket: swap main_mem and io regions

The total size of RAM (main_mem) can be expected to vary significantly,
and often exceed the size needed for MMIO allocations by a large margin.

As such, place Rocket's MMIO (io regions) below 0x8000_0000, and start
the RAM (main_mem) at 0x8000_0000, with nothing above it to limit its
future growth.

Also, bump the pre-built Rocket verilog submodule to an updated version,
which also comes with matching changes to the way MMIO and RAM accesses
are mapped and routed to their respective AXI interfaces.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
---

diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 54c31596..c9fdb0dd 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -56,15 +56,17 @@ class RocketRV64(CPU):
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf")
     linker_output_format = "elf64-littleriscv"
-    io_regions           = {0x80000000: 0x80000000} # origin, length
+    io_regions           = {0x10000000: 0x70000000} # origin, length
 
     @property
     def mem_map(self):
         # Rocket reserves the first 256Mbytes for internal use, so we must change default mem_map.
         return {
-            "rom"  : 0x10000000,
-            "sram" : 0x11000000,
-            "csr"  : 0x92000000,
+            "rom"      : 0x10000000,
+            "sram"     : 0x11000000,
+            "csr"      : 0x12000000,
+            "ethmac"   : 0x30000000,
+            "main_ram" : 0x80000000,
         }
 
     @property
diff --git a/litex/soc/cores/cpu/rocket/verilog b/litex/soc/cores/cpu/rocket/verilog
index b17b6984..d67a7d7a 160000
--- a/litex/soc/cores/cpu/rocket/verilog
+++ b/litex/soc/cores/cpu/rocket/verilog
@@ -1 +1 @@
-Subproject commit b17b6984b9b7b0d0c259306ba94187abae7f37f5
+Subproject commit d67a7d7a12ff06297226b1862412849c4d50e949