From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 5 Oct 2019 15:57:37 +0000 (-0700)
Subject: Missed this
X-Git-Tag: working-ls180~1003^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f90a4b1e24e36943a343bd36315b6029dd6cd044;p=yosys.git

Missed this
---

diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index 2408d483a..a57043009 100644
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -105,9 +105,10 @@ endcode
 // #######################
 
 // Subpattern for matching against input registers, based on knowledge of the
-//   'Q' input. Typically, this task would be handled by other Yosys passes
-//   such as dff2dffe, but since DSP inference happens much before this, these
-//   patterns have to be manually identified.
+//   'Q' input. Typically, identifying registers with clock-enable and reset
+//   capability would be a task would be handled by other Yosys passes such as
+//   dff2dffe, but since DSP inference happens much before this, these patterns
+//   have to be manually identified.
 // At a high level:
 //   (1) Starting from a $dff cell that (partially or fully) drives the given
 //       'Q' argument