From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Nov 2013 12:19:04 +0000 (+0100)
Subject: Added roadmap to readme file
X-Git-Tag: yosys-0.2.0~422
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f912e029de64b17316c2d285bf728151e6bd6de3;p=yosys.git

Added roadmap to readme file
---

diff --git a/README b/README
index 9d48f5d86..ef482b0f1 100644
--- a/README
+++ b/README
@@ -280,6 +280,15 @@ and after each occurrence of PRIi64 in the header file:
 	 sudo sed -i 's/PRIi64/ & /' /usr/include/minisat/utils/Options.h
 
 
+Roadmap / Large-scale TODOs
+===========================
+
+- Technology mapping for real-world applications (specific FPGAs and ASIC processes)
+- Improve standard complience of const folding and parameters (mostly expression widths)
+- Implement SAT-based formal equivialence checker based on existing SAT framework
+- Re-implement Verilog frontend (cleaner AST format, pipeline of well structured AST transformations)
+
+
 TODOs / Open Bugs
 =================