From: lkcl <lkcl@web>
Date: Fri, 30 Aug 2019 10:37:29 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4186
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f915cac717527afc4982b4430398556825022d51;p=libreriscv.git

---

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index 15d7d11d6..0c144fccf 100644
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -7,7 +7,7 @@ Thus it makes more sense to actually *use* one of the scalar registers *as* VL.
 
 Format for Vector Configuration Instructions under OP-V major opcode:
 
-| 31|30   20|19    15|14..12|11 7|6     0| name       |
+| 31|30...20|19....15|14..12|11 7|6.....0| name       |
 |---|-------|--------|------|----|-------|------------|
 | 0 | VLMAX | rs1    | 111  | rd |1010111| sv.setvl   |
 | 0 | VLMAX | 0 (x0) | 111  | rd |1010111| sv.setvl   |