From: Kito Cheng <kito.cheng@gmail.com>
Date: Wed, 5 Apr 2017 12:58:28 +0000 (+0800)
Subject: RISC-V: Fix disassemble for c.li, c.andi and c.addiw
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f91d48deb29d9e6f4b530f586db0140943ed0d83;p=binutils-gdb.git

RISC-V: Fix disassemble for c.li, c.andi and c.addiw

ChangeLog

2017-05-03  Kito Cheng  <kito.cheng@gmail.com>

        * riscv-dis.c (print_insn_args): Handle 'Co' operands.
---

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 355a162b0ec..ea0902fc1d4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
+
+	* riscv-dis.c (print_insn_args): Handle 'Co' operands.
+
 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 
 	* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d760d701d49..bb534633102 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 	    case 'i':
 	      print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
 	      break;
+	    case 'o':
 	    case 'j':
 	      print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
 	      break;