From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Feb 2020 14:35:11 +0000 (+0000)
Subject: zero bitmask in Shifter
X-Git-Tag: ls180-24jan2020~125
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f91d882893e74b0c26c06ad92221d69d768911d6;p=ieee754fpu.git

zero bitmask in Shifter
---

diff --git a/src/ieee754/part_shift/part_shift_dynamic.py b/src/ieee754/part_shift/part_shift_dynamic.py
index 93188618..7e5134fd 100644
--- a/src/ieee754/part_shift/part_shift_dynamic.py
+++ b/src/ieee754/part_shift/part_shift_dynamic.py
@@ -42,6 +42,7 @@ class ShifterMask(Elaboratable):
         bl = []
         for j in range(self.pwid):
             bit = Signal(self.pwid, name="bit%d" % j, reset_less=True)
+            comb += bit.eq(C(0, self.pwid))
             if j != 0:
                 comb += bit.eq((~self.gates[j]) & bl[j-1])
             else:
@@ -50,7 +51,7 @@ class ShifterMask(Elaboratable):
         # XXX ARGH, really annoying: simulation bug, can't use Cat(*bl).
         for j in range(bits.shape()[0]):
             comb += bits[j].eq(bl[j])
-        comb += self.mask.eq(Cat(minm, bits) & maxm)
+        comb += self.mask.eq(Cat(minm, bits) & C(maxm, self.mask.shape()))
 
         return m