From: Dmitry Selyutin Date: Wed, 31 May 2023 19:25:32 +0000 (+0300) Subject: power_enums: provide selector type property X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f926a48c1fd952f290f62cf78ece4d75374547fc;p=openpower-isa.git power_enums: provide selector type property --- diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 5be81808..66298f98 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -974,6 +974,12 @@ class In1Sel(Enum): CIA = 8 # for addpcis RT = 9 + @property + def type(self): + if self is In1Sel.NONE: + return SelType.NONE + return SelType.SRC + class In2Sel(Enum): NONE = 0 @@ -999,6 +1005,12 @@ class In2Sel(Enum): CONST_DXHI4 = 18 # for addpcis CONST_DQ = 19 # for ld/st-quad + @property + def type(self): + if self is In2Sel.NONE: + return SelType.NONE + return SelType.SRC + class In3Sel(Enum): NONE = 0 @@ -1013,6 +1025,12 @@ class In3Sel(Enum): RTp = RT FRA = 7 + @property + def type(self): + if self is In3Sel.NONE: + return SelType.NONE + return SelType.SRC + class OutSel(Enum): NONE = 0 @@ -1029,6 +1047,12 @@ class OutSel(Enum): RSp = RS FRA = 8 + @property + def type(self): + if self is OutSel.NONE: + return SelType.NONE + return SelType.DST + @unique class LDSTLen(Enum): @@ -1078,12 +1102,24 @@ class CRInSel(Enum): CR1 = 7 BA = 8 + @property + def type(self): + if self is CRInSel.NONE: + return SelType.NONE + return SelType.SRC + @unique class CRIn2Sel(Enum): NONE = 0 BB = 1 + @property + def type(self): + if self is CRIn2Sel.NONE: + return SelType.NONE + return SelType.SRC + @unique class CROutSel(Enum): @@ -1094,6 +1130,12 @@ class CROutSel(Enum): WHOLE_REG = 4 CR1 = 5 + @property + def type(self): + if self is CROutSel.NONE: + return SelType.NONE + return SelType.DST + # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and # http://libre-riscv.org/openpower/isatables/sprs.csv