From: Sergi Granell <xerpi.g.12@gmail.com>
Date: Tue, 27 Mar 2018 07:35:20 +0000 (+0200)
Subject: passes/hierarchy: Reduce code duplication in expand_module
X-Git-Tag: yosys-0.8~142^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f93f8aaa114b06e046a107c9e1f77046a4b5b1fc;p=yosys.git

passes/hierarchy: Reduce code duplication in expand_module

This also makes it easier to add new file extensions support.

Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 71b0cf622..21a232572 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -173,22 +173,20 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 
 			for (auto &dir : libdirs)
 			{
-				filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v";
-				if (check_file_exists(filename)) {
-					Frontend::frontend_call(design, NULL, filename, "verilog");
-					goto loaded_module;
-				}
-
-				filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".sv";
-				if (check_file_exists(filename)) {
-					Frontend::frontend_call(design, NULL, filename, "verilog -sv");
-					goto loaded_module;
-				}
+				static const std::map<std::string, std::string> extensions_map =
+				{
+					{".v", "verilog"},
+					{".sv", "verilog -sv"},
+					{".il", "ilang"}
+				};
 
-				filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il";
-				if (check_file_exists(filename)) {
-					Frontend::frontend_call(design, NULL, filename, "ilang");
-					goto loaded_module;
+				for (auto &ext : extensions_map)
+				{
+					filename = dir + "/" + RTLIL::unescape_id(cell->type) + ext.first;
+					if (check_file_exists(filename)) {
+						Frontend::frontend_call(design, NULL, filename, ext.second);
+						goto loaded_module;
+					}
 				}
 			}