From: Xan <Xan@web>
Date: Wed, 25 Apr 2018 04:53:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5566
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f94c47f90eee4871134dae5975079388e1b43fd4;p=libreriscv.git

---

diff --git a/Harmonised_RVV/Packed_SIMD.mdwn b/Harmonised_RVV/Packed_SIMD.mdwn
index d089b7f13..f720761a9 100644
--- a/Harmonised_RVV/Packed_SIMD.mdwn
+++ b/Harmonised_RVV/Packed_SIMD.mdwn
@@ -38,7 +38,7 @@ However, note RV32I registers can fit 4x INT8 elements.  To preserve Andes SIMD
 
 A programmer can configure VCFG with the any mix of these alternative configurations:
 
-*  v0-v31 are all INT 16, and MVL is same as point #4 above
+*  v0-v31 are all INT 16, and MVL is same as for Default MVL above
 *  v0-v31 are all INT 8 and MVL is 4 on RV32I and 8 on RV64I
 *  A lesser number of registers (<v31) could be supported, eg. default is only v0-v29 defined.  (Accessing registers beyond maximum defined by VDCFG is to be legal, with a type of INT32 assumed.  However, this is not to affect the MVL, which is to be calculated based on INT8/INT16 vectors only)
 *  With the above alternative configs, there can be any split between signed & unsigned.