From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 10:41:41 +0000 (+0200)
Subject: Remove not needed tests
X-Git-Tag: working-ls180~987^2~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f94dc2c072572f5b4316cb26415e7a3a4183c362;p=yosys.git

Remove not needed tests
---

diff --git a/tests/efinix/alu.v b/tests/efinix/alu.v
deleted file mode 100644
index f82cc2e21..000000000
--- a/tests/efinix/alu.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module top (
-	input clock,
-	input [31:0] dinA, dinB,
-	input [2:0] opcode,
-	output reg [31:0] dout
-);
-	always @(posedge clock) begin
-		case (opcode)
-		0: dout <= dinA + dinB;
-		1: dout <= dinA - dinB;
-		2: dout <= dinA >> dinB;
-		3: dout <= $signed(dinA) >>> dinB;
-		4: dout <= dinA << dinB;
-		5: dout <= dinA & dinB;
-		6: dout <= dinA | dinB;
-		7: dout <= dinA ^ dinB;
-		endcase
-	end
-endmodule
diff --git a/tests/efinix/alu.ys b/tests/efinix/alu.ys
deleted file mode 100644
index 0d58a7c8a..000000000
--- a/tests/efinix/alu.ys
+++ /dev/null
@@ -1,13 +0,0 @@
-read_verilog alu.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 66  t:EFX_ADD
-select -assert-count 1   t:EFX_GBUFCE
-select -assert-count 32  t:EFX_FF
-select -assert-count 605 t:EFX_LUT4
-select -assert-none t:EFX_ADD t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
diff --git a/tests/efinix/div_mod.v b/tests/efinix/div_mod.v
deleted file mode 100644
index 64a36707d..000000000
--- a/tests/efinix/div_mod.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x % y;
-assign B =  x / y;
-
-endmodule
diff --git a/tests/efinix/div_mod.ys b/tests/efinix/div_mod.ys
deleted file mode 100644
index 3b6f2f0f4..000000000
--- a/tests/efinix/div_mod.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog div_mod.v
-hierarchy -top top
-flatten
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 95  t:EFX_ADD
-select -assert-count 114 t:EFX_LUT4
-select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
diff --git a/tests/efinix/mul.v b/tests/efinix/mul.v
deleted file mode 100644
index 0f1618698..000000000
--- a/tests/efinix/mul.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top
-(
- input [7:0] x,
- input [7:0] y,
-
- output [15:0] A,
- );
-
-assign A =  x * y;
-
-endmodule
diff --git a/tests/efinix/mul.ys b/tests/efinix/mul.ys
deleted file mode 100644
index 7d349f3f8..000000000
--- a/tests/efinix/mul.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog mul.v
-hierarchy -top top
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 17  t:EFX_ADD
-select -assert-count 149 t:EFX_LUT4
-select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D