From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 13 Nov 2021 14:41:51 +0000 (+0000)
Subject: start adding hazard vector setting in core (unfinished)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f94e0b14e7f28311cc068000e139e0eae0081088;p=soc.git

start adding hazard vector setting in core (unfinished)
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 80829761..6a8f3e81 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -550,6 +550,15 @@ class NonProductionCore(ControlBase):
                       dest.shape(), wport.i_data.shape())
                 wsigs.append(fu_dest_latch)
 
+                # now connect up the bitvector write hazard
+                if not self.make_hazard_vecs:
+                    continue
+                wv = regs.wv[regfile.lower()]
+                wvport = wv.w_ports[rpidx]
+                comb += wvport.i_data.eq(1) # always enable, for now
+                print ("write vector", regfile, wvport)
+                #if rfile.unary:
+
         # here is where we create the Write Broadcast Bus. simple, eh?
         comb += wport.i_data.eq(ortreereduce_sig(wsigs))
         if rfile.unary: