From: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue, 20 Nov 2018 19:20:27 +0000 (-0800)
Subject: iris: RT flush for memorybarrier with texture bit
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9612e7682541d28ea0a2a7f4e26718f17ed1b3d;p=mesa.git

iris: RT flush for memorybarrier with texture bit

PIXEL_BUFFER_BARRIER_BIT turns into PIPE_BARRIER_TEXTURE and it ought
to trigger an RT flush, according to brw_memory_barrier
---

diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c
index 5e5a996e40b..52e842bc661 100644
--- a/src/gallium/drivers/iris/iris_pipe_control.c
+++ b/src/gallium/drivers/iris/iris_pipe_control.c
@@ -184,17 +184,11 @@ iris_memory_barrier(struct pipe_context *ctx, unsigned flags)
               PIPE_CONTROL_CONST_CACHE_INVALIDATE;
    }
 
-   if (flags & PIPE_BARRIER_TEXTURE) {
-      bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
-   }
-
-   if (flags & PIPE_BARRIER_FRAMEBUFFER) {
+   if (flags & (PIPE_BARRIER_TEXTURE | PIPE_BARRIER_FRAMEBUFFER)) {
       bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
               PIPE_CONTROL_RENDER_TARGET_FLUSH;
    }
 
-   // XXX: MAPPED_BUFFER, QUERY_BUFFER, STREAMOUT_BUFFER, GLOBAL_BUFFER?
-
    // XXX: don't unconditionally emit flushes in both engines, we don't
    // even know if we're even using e.g. the compute engine...