From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 00:27:26 +0000 (+0000)
Subject: make FPADDBasePipe derive from ControlBase
X-Git-Tag: ls180-24jan2020~1451
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f968e27def692e22230fa35ff9db5287a33e8945;p=ieee754fpu.git

make FPADDBasePipe derive from ControlBase
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index c9319f55..a175de31 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -9,7 +9,7 @@ from math import log
 
 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
 from fpbase import MultiShiftRMerge, Trigger
-from example_buf_pipe import StageChain, UnbufferedPipeline
+from singlepipe import (ControlBase, StageChain, UnbufferedPipeline)
 #from fpbase import FPNumShiftMultiRight
 
 
@@ -1874,16 +1874,16 @@ class FPAddBaseStage:
         return o
 
 
-class FPADDBasePipe:
+class FPADDBasePipe(ControlBase):
     def __init__(self, width, id_wid):
-        stage1 = FPAddBaseStage(width, id_wid)
-        self.pipe = UnbufferedPipeline(stage1)
+        ControlBase.__init__(self)
 
     def elaborate(self, platform):
-        return self.pipe.elaborate(platform)
+        m = Module()
+        stage1 = FPAddBaseStage(width, id_wid)
+        m.d.comb += self.connect([stage1])
+        return m
 
-    def ports(self):
-        return self.pipe.ports()
 
 class ResArray:
     def __init__(self, width, id_wid):