From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 05:33:35 +0000 (-0700)
Subject: Another typo
X-Git-Tag: working-ls180~881^2^2~264
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f984e0cb345c7cec85eb9b90a13faacffa2e3fa2;p=yosys.git

Another typo
---

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 8e0b578ab..e4937f646 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -112,7 +112,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
       \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
   endgenerate
 endmodule
-module FDPE_1 (output reg Q, input C, CE, D, CLR);
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
   \$__ABC_FDPE_1 #(