From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Dec 2021 14:11:45 +0000 (+0000)
Subject: global (one) do_read signal in cache_rams dcache.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f991444eb0789507f48c48bb63a4f0af95a33563;p=soc.git

global (one) do_read signal in cache_rams dcache.py
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index a93aa92e..9b743cd0 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1133,8 +1133,10 @@ class DCache(Elaboratable):
         comb += hit_req_way_onehot.eq(1<<r1.req.hit_way)
         comb += replace_way_onehot.eq(1<<replace_way)
 
+        do_read  = Signal()
+        comb += do_read.eq(1)
+
         for i in range(NUM_WAYS):
-            do_read  = Signal(name="do_rd%d" % i)
             rd_addr  = Signal(ROW_BITS, name="rd_addr_%d" % i)
             do_write = Signal(name="do_wr%d" % i)
             wr_addr  = Signal(ROW_BITS, name="wr_addr_%d" % i)
@@ -1154,7 +1156,6 @@ class DCache(Elaboratable):
             comb += way.wr_data.eq(wr_data)
 
             # Cache hit reads
-            comb += do_read.eq(1)
             comb += rd_addr.eq(early_req_row)
             with m.If(hit_way_onehot[i]):
                 comb += cache_out_row.eq(_d_out)