From: Michael Nolan <mtnolan2640@gmail.com>
Date: Mon, 11 May 2020 14:23:00 +0000 (-0400)
Subject: Re-enable rlwinm test
X-Git-Tag: div_pipeline~1284
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f993b9071a09b0fe4e62e25246fcc4f1f2115c9e;p=soc.git

Re-enable rlwinm test
---

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index d3ec23ab..9d44730d 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -178,7 +178,6 @@ class ALUTestCase(FHDLTestCase):
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
 
-    @unittest.skip("broken")
     def test_rlwinm(self):
         for i in range(10):
             mb = random.randint(0,31)
@@ -192,15 +191,13 @@ class ALUTestCase(FHDLTestCase):
 
     @unittest.skip("broken")
     def test_rlwimi(self):
-        lst = ["rlwinm 3, 1, 5, 20, 6",
-               "rlwimi 3, 1, 5, 20, 6"]
+        lst = ["rlwimi 3, 1, 5, 20, 6"]
         initial_regs = [0] * 32
-        initial_regs[1] = random.randint(0, (1<<64)-1)
-        initial_regs[3] = random.randint(0, (1<<64)-1)
+        initial_regs[1] = 0xdeadbeef
+        initial_regs[3] = 0x12345678
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
 
-    @unittest.skip("broken")
     def test_rlwnm(self):
         lst = ["rlwnm 3, 1, 2, 20, 6"]
         initial_regs = [0] * 32
diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 5834df40..29ebb5d6 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -194,7 +194,7 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[2] = 5
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
-            self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 32))
+            self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 64))
 
     def test_srw(self):
         lst = ["srw 1, 3, 2"]
@@ -203,7 +203,7 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[2] = 5
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
-            self.assertEqual(sim.gpr(1), SelectableInt(0x657f5d5, 32))
+            self.assertEqual(sim.gpr(1), SelectableInt(0x657f5d5, 64))
 
     def test_rlwinm(self):
         lst = ["rlwinm 3, 1, 5, 20, 6"]
@@ -213,6 +213,15 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_regs)
             self.assertEqual(sim.gpr(3), SelectableInt(0xfe000fff, 64))
 
+    def test_rlwimi(self):
+        lst = ["rlwimi 3, 1, 5, 20, 6"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xdeadbeef
+        initial_regs[3] = 0x12345678
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(3), SelectableInt(0xd4345dfb, 64))
+
     def test_mtcrf(self):
         for i in range(4):
             # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for