From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 24 Jun 2020 09:01:06 +0000 (+0200)
Subject: verific - import attributes for net buses as well
X-Git-Tag: working-ls180~450^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f993d1875565c329689815a3bf63c6db76774c15;p=yosys.git

verific - import attributes for net buses as well
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1630c57bc..89d734c40 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1109,7 +1109,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 			RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
 			wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
-			import_attributes(wire->attributes, netbus, nl);
+			MapIter mibus;
+			FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
+				import_attributes(wire->attributes, net, nl);
+			}
 
 			RTLIL::Const initval = Const(State::Sx, GetSize(wire));
 			bool initval_valid = false;