From: Clifford Wolf Date: Sat, 26 Jul 2014 23:49:51 +0000 (+0200) Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ X-Git-Tag: yosys-0.4~407 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9946232adf887e5aa4a48c64f88eaa17e424009;p=yosys.git Refactoring: Renamed RTLIL::Module::wires to wires_ --- diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc index db49880ae..06b2c2a93 100644 --- a/backends/autotest/autotest.cc +++ b/backends/autotest/autotest.cc @@ -105,7 +105,7 @@ static void autotest(FILE *f, RTLIL::Design *design) int count_ports = 0; log("Generating test bench for module `%s'.\n", it->first.c_str()); - for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) { + for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) { RTLIL::Wire *wire = it2->second; if (wire->port_output) { count_ports++; @@ -134,7 +134,7 @@ static void autotest(FILE *f, RTLIL::Design *design) } } fprintf(f, "%s %s(\n", id(mod->name).c_str(), idy("uut", mod->name).c_str()); - for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) { + for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) { RTLIL::Wire *wire = it2->second; if (wire->port_output || wire->port_input) fprintf(f, "\t.%s(%s)%s\n", id(wire->name).c_str(), diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index cb40834b3..7ae9965d5 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -103,7 +103,7 @@ struct BlifDumper std::map inputs, outputs; - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_input) inputs[wire->port_id] = wire; diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index f731e17e2..f1e95ee15 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -80,7 +80,7 @@ struct BtorDumper { line_num=0; str.clear(); - for(auto it=module->wires.begin(); it!=module->wires.end(); ++it) + for(auto it=module->wires_.begin(); it!=module->wires_.end(); ++it) { if(it->second->port_input) { @@ -880,7 +880,7 @@ struct BtorDumper std::map inputs, outputs; std::vector safety; - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_input) inputs[wire->port_id] = wire; diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index fc2f4a7e4..e99d094f7 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -255,7 +255,7 @@ struct EdifBackend : public Backend { fprintf(f, " (view VIEW_NETLIST\n"); fprintf(f, " (viewType NETLIST)\n"); fprintf(f, " (interface\n"); - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) continue; diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 6678f19d2..c0b7dab9a 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -280,7 +280,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module if (print_body) { - for (auto it = module->wires.begin(); it != module->wires.end(); it++) + for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) if (!only_selected || design->selected(module, it->second)) { if (only_selected) fprintf(f, "\n"); diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 8c08747c3..4e8c321bb 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -147,7 +147,7 @@ struct IntersynthBackend : public Backend { netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name)); // Module Ports: "std::set celltypes_code" prevents duplicate top level ports - for (auto wire_it : module->wires) { + for (auto wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_input || wire->port_output) { celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n", diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 077368771..ef31e06a9 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -68,7 +68,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de RTLIL::Module *mod = design->modules.at(cell->type); std::vector ports; - for (auto wire_it : mod->wires) { + for (auto wire_it : mod->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) continue; @@ -195,7 +195,7 @@ struct SpiceBackend : public Backend { } std::vector ports; - for (auto wire_it : module->wires) { + for (auto wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) continue; diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d9186c043..5e98a4c54 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -76,7 +76,7 @@ void reset_auto_counter(RTLIL::Module *module) reset_auto_counter_id(module->name, false); - for (auto it = module->wires.begin(); it != module->wires.end(); it++) + for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) reset_auto_counter_id(it->second->name, true); for (auto it = module->cells.begin(); it != module->cells.end(); it++) { @@ -920,7 +920,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) reg_bits.insert(std::pair(chunk.wire, chunk.offset+i)); } } - for (auto &it : module->wires) + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) @@ -936,7 +936,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) bool keep_running = true; for (int port_id = 1; keep_running; port_id++) { keep_running = false; - for (auto it = module->wires.begin(); it != module->wires.end(); it++) { + for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) { RTLIL::Wire *wire = it->second; if (wire->port_id == port_id) { if (port_id != 1) @@ -949,7 +949,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) } fprintf(f, ");\n"); - for (auto it = module->wires.begin(); it != module->wires.end(); it++) + for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) dump_wire(f, indent + " ", it->second); for (auto it = module->memories.begin(); it != module->memories.end(); it++) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 3bc9b06ee..064aec93f 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -296,7 +296,7 @@ struct AST_INTERNAL::ProcessGenerator chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);; if (chunk.wire->name.find('$') != std::string::npos) wire_name += stringf("$%d", RTLIL::autoidx++); - } while (current_module->wires.count(wire_name) > 0); + } while (current_module->wires_.count(wire_name) > 0); RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width); wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum); @@ -779,7 +779,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // create an RTLIL::Wire for an AST_WIRE node case AST_WIRE: { - if (current_module->wires.count(str) != 0) + if (current_module->wires_.count(str) != 0) log_error("Re-definition of signal `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); if (!range_valid) @@ -869,7 +869,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Wire *wire = NULL; RTLIL::SigChunk chunk; - if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires.count(str) == 0) { + if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) { RTLIL::Wire *wire = current_module->addWire(str); wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->name = str; @@ -886,7 +886,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) goto use_const_chunk; } else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE && - id2ast->type != AST_MEMORY) || current_module->wires.count(str) == 0) + id2ast->type != AST_MEMORY) || current_module->wires_.count(str) == 0) log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n", str.c_str(), filename.c_str(), linenum); @@ -894,7 +894,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n", str.c_str(), filename.c_str(), linenum); - wire = current_module->wires[str]; + wire = current_module->wires_[str]; chunk.wire = wire; chunk.width = wire->width; chunk.offset = 0; diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index d7068d468..c476de87a 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -45,11 +45,11 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1; std::string id = RTLIL::escape_id(std::string(expr, id_len)); - if (!module->wires.count(id)) + if (!module->wires_.count(id)) log_error("Can't resolve wire name %s.\n", RTLIL::id2cstr(id)); expr += id_len; - return module->wires.at(id); + return module->wires_.at(id); } static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A) @@ -527,7 +527,7 @@ struct LibertyFrontend : public Frontend { if (flag_lib && dir->value == "internal") continue; - RTLIL::Wire *wire = module->wires.at(RTLIL::escape_id(node->args.at(0))); + RTLIL::Wire *wire = module->wires_.at(RTLIL::escape_id(node->args.at(0))); if (dir && dir->value == "inout") { wire->port_input = true; diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 769145838..d3c848f46 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -181,8 +181,8 @@ struct CellTypes if (cell_types.count(type) == 0) { for (auto design : designs) if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires.count(port)) - return design->modules.at(type)->wires.at(port)->port_output; + if (design->modules.at(type)->wires_.count(port)) + return design->modules.at(type)->wires_.at(port)->port_output; return false; } return false; @@ -204,8 +204,8 @@ struct CellTypes if (cell_types.count(type) == 0) { for (auto design : designs) if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires.count(port)) - return design->modules.at(type)->wires.at(port)->port_input; + if (design->modules.at(type)->wires_.count(port)) + return design->modules.at(type)->wires_.at(port)->port_input; return false; } return false; diff --git a/kernel/driver.cc b/kernel/driver.cc index 97910aa98..3fbb96580 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -243,7 +243,7 @@ static char *readline_obj_generator(const char *text, int state) { RTLIL::Module *module = design->modules.at(design->selected_active_module); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); diff --git a/kernel/modwalker.h b/kernel/modwalker.h index a3983a2c1..a90d739eb 100644 --- a/kernel/modwalker.h +++ b/kernel/modwalker.h @@ -121,7 +121,7 @@ struct ModWalker signal_inputs.clear(); signal_outputs.clear(); - for (auto &it : module->wires) + for (auto &it : module->wires_) add_wire(it.second); for (auto &it : module->cells) if (filter_ct == NULL || filter_ct->cell_known(it.second->type)) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 240bbc6be..0cfcf018c 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -203,7 +203,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) for (auto &it : selected_members) if (it.second.size() == 0) del_list.push_back(it.first); - else if (it.second.size() == design->modules[it.first]->wires.size() + design->modules[it.first]->memories.size() + + else if (it.second.size() == design->modules[it.first]->wires_.size() + design->modules[it.first]->memories.size() + design->modules[it.first]->cells.size() + design->modules[it.first]->processes.size()) add_list.push_back(it.first); for (auto mod_name : del_list) @@ -276,7 +276,7 @@ bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString me RTLIL::Module::~Module() { - for (auto it = wires.begin(); it != wires.end(); it++) + for (auto it = wires_.begin(); it != wires_.end(); it++) delete it->second; for (auto it = memories.begin(); it != memories.end(); it++) delete it->second; @@ -293,7 +293,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::mapname); assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); assert(it.second->width >= 0); @@ -776,7 +776,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const new_mod->connections_ = connections_; new_mod->attributes = attributes; - for (auto &it : wires) + for (auto &it : wires_) new_mod->addWire(it.first, it.second); for (auto &it : memories) @@ -796,7 +796,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const std::vector chunks = sig.chunks(); for (auto &c : chunks) if (c.wire != NULL) - c.wire = mod->wires.at(c.wire->name); + c.wire = mod->wires_.at(c.wire->name); sig = chunks; } }; @@ -817,7 +817,7 @@ void RTLIL::Module::add(RTLIL::Wire *wire) { assert(!wire->name.empty()); assert(count_id(wire->name) == 0); - wires[wire->name] = wire; + wires_[wire->name] = wire; } void RTLIL::Module::add(RTLIL::Cell *cell) @@ -848,9 +848,9 @@ namespace { #if 0 void RTLIL::Module::remove(RTLIL::Wire *wire) { - std::set wires; - wires.insert(wire); - remove(wires); + std::set wires_; + wires_.insert(wire); + remove(wires_); } #endif @@ -862,7 +862,7 @@ void RTLIL::Module::remove(const std::set &wires) rewrite_sigspecs(delete_wire_worker); for (auto &it : wires) { - this->wires.erase(it->name); + this->wires_.erase(it->name); delete it; } } @@ -876,8 +876,8 @@ void RTLIL::Module::remove(RTLIL::Cell *cell) void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) { - assert(wires[wire->name] == wire); - wires.erase(wire->name); + assert(wires_[wire->name] == wire); + wires_.erase(wire->name); wire->name = new_name; add(wire); } @@ -893,8 +893,8 @@ void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name) void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name) { assert(count_id(old_name) != 0); - if (wires.count(old_name)) - rename(wires.at(old_name), new_name); + if (wires_.count(old_name)) + rename(wires_.at(old_name), new_name); else if (cells.count(old_name)) rename(cells.at(old_name), new_name); else @@ -932,7 +932,7 @@ void RTLIL::Module::fixup_ports() { std::vector all_ports; - for (auto &w : wires) + for (auto &w : wires_) if (w.second->port_input || w.second->port_output) all_ports.push_back(w.second); else @@ -2457,7 +2457,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri if (netname[0] != '$' && netname[0] != '\\') netname = "\\" + netname; - if (module->wires.count(netname) == 0) { + if (module->wires_.count(netname) == 0) { size_t indices_pos = netname.size()-1; if (indices_pos > 2 && netname[indices_pos] == ']') { @@ -2474,10 +2474,10 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri } } - if (module->wires.count(netname) == 0) + if (module->wires_.count(netname) == 0) return false; - RTLIL::Wire *wire = module->wires.at(netname); + RTLIL::Wire *wire = module->wires_.at(netname); if (!indices.empty()) { std::vector index_tokens; sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); @@ -2514,7 +2514,7 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL sig = RTLIL::SigSpec(); RTLIL::Selection &sel = design->selection_vars.at(str); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (sel.selected_member(module->name, it.first)) sig.append(it.second); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index cbb612473..1d040975b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -280,7 +280,7 @@ protected: public: RTLIL::IdString name; std::set avail_parameters; - std::map wires; + std::map wires_; std::map memories; std::map cells; std::map processes; diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index f67ffe1e8..9eacfbcb5 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -43,7 +43,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re } // for each wire in the module - for (auto &wire_iter : module->wires) + for (auto &wire_iter : module->wires_) { RTLIL::Wire *wire = wire_iter.second; diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc index cf8a4add8..0cd1da808 100644 --- a/manual/PRESENTATION_Prog/my_cmd.cc +++ b/manual/PRESENTATION_Prog/my_cmd.cc @@ -14,7 +14,7 @@ struct MyPass : public Pass { log("Modules in current design:\n"); for (auto &mod : design->modules) log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first), - mod.second->wires.size(), mod.second->cells.size()); + mod.second->wires_.size(), mod.second->cells.size()); } } MyPass; @@ -58,8 +58,8 @@ struct Test2Pass : public Pass { RTLIL::Module *module = design->modules.at("\\test"); - RTLIL::SigSpec a(module->wires.at("\\a")), x(module->wires.at("\\x")), - y(module->wires.at("\\y")); + RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")), + y(module->wires_.at("\\y")); log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0" SigMap sigmap(module); diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 41cfe88f6..184f143a1 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -453,8 +453,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_polarity = false; clk_str = clk_str.substr(1); } - if (module->wires.count(RTLIL::escape_id(clk_str)) != 0) - clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 0)); + if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0) + clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0)); } if (dff_mode && clk_sig.size() == 0) @@ -495,7 +495,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto c : cells) extract_cell(c, keepff); - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep")) mark_port(RTLIL::SigSpec(wire_it.second)); } @@ -687,7 +687,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Module *mapped_mod = mapped_design->modules["\\netlist"]; if (mapped_mod == NULL) log_error("ABC output file does not contain a module `netlist'.\n"); - for (auto &it : mapped_mod->wires) { + for (auto &it : mapped_mod->wires_) { RTLIL::Wire *w = it.second; RTLIL::Wire *wire = module->addWire(remap_name(w->name)); design->select(module, wire); @@ -701,47 +701,47 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); module->connect(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]); - conn.second = RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]); + conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]); module->connect(conn); continue; } if (c->type == "\\INV") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_"); - cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)])); - cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)])); + cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)])); + cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); - cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)])); - cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)])); - cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)])); + cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)])); + cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)])); + cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\MUX") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_"); - cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)])); - cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)])); - cell->set("\\S", RTLIL::SigSpec(module->wires[remap_name(c->get("\\S").as_wire()->name)])); - cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)])); + cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)])); + cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)])); + cell->set("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\S").as_wire()->name)])); + cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\DFF") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)])); - cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)])); + cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)])); + cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)])); cell->set("\\C", clk_sig); design->select(module, cell); continue; @@ -757,7 +757,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections().begin()->second.as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); module->connect(conn); continue; @@ -765,8 +765,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std if (c->type == "\\_dff_") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)])); - cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)])); + cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)])); + cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)])); cell->set("\\C", clk_sig); design->select(module, cell); continue; @@ -779,7 +779,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std if (c.width == 0) continue; assert(c.width == 1); - newsig.append(module->wires[remap_name(c.wire->name)]); + newsig.append(module->wires_[remap_name(c.wire->name)]); } cell->set(conn.first, newsig); } @@ -789,9 +789,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto conn : mapped_mod->connections()) { if (!conn.first.is_fully_const()) - conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(conn.first.as_wire()->name)]); if (!conn.second.is_fully_const()) - conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.as_wire()->name)]); + conn.second = RTLIL::SigSpec(module->wires_[remap_name(conn.second.as_wire()->name)]); module->connect(conn); } @@ -805,10 +805,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::SigSig conn; if (si.type >= 0) { conn.first = si.bit; - conn.second = RTLIL::SigSpec(module->wires[remap_name(buffer)]); + conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]); out_wires++; } else { - conn.first = RTLIL::SigSpec(module->wires[remap_name(buffer)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]); conn.second = si.bit; in_wires++; } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index e86afa1b7..773bbe5d2 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -113,15 +113,15 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) char *d = strtok(NULL, " \t\r\n"); char *q = strtok(NULL, " \t\r\n"); - if (module->wires.count(RTLIL::escape_id(d)) == 0) + if (module->wires_.count(RTLIL::escape_id(d)) == 0) module->addWire(RTLIL::escape_id(d)); - if (module->wires.count(RTLIL::escape_id(q)) == 0) + if (module->wires_.count(RTLIL::escape_id(q)) == 0) module->addWire(RTLIL::escape_id(q)); RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name); - cell->set("\\D", module->wires.at(RTLIL::escape_id(d))); - cell->set("\\Q", module->wires.at(RTLIL::escape_id(q))); + cell->set("\\D", module->wires_.at(RTLIL::escape_id(d))); + cell->set("\\Q", module->wires_.at(RTLIL::escape_id(q))); continue; } @@ -138,9 +138,9 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) if (q == NULL || !q[0] || !q[1]) goto error; *(q++) = 0; - if (module->wires.count(RTLIL::escape_id(q)) == 0) + if (module->wires_.count(RTLIL::escape_id(q)) == 0) module->addWire(RTLIL::escape_id(q)); - cell->set(RTLIL::escape_id(p), module->wires.at(RTLIL::escape_id(q))); + cell->set(RTLIL::escape_id(p), module->wires_.at(RTLIL::escape_id(q))); } continue; } @@ -151,8 +151,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::SigSpec input_sig, output_sig; while ((p = strtok(NULL, " \t\r\n")) != NULL) { RTLIL::Wire *wire; - if (module->wires.count(stringf("\\%s", p)) > 0) { - wire = module->wires.at(stringf("\\%s", p)); + if (module->wires_.count(stringf("\\%s", p)) > 0) { + wire = module->wires_.at(stringf("\\%s", p)); } else { wire = module->addWire(stringf("\\%s", p)); } diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 7e9ba97ec..e97bf8fc1 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -28,8 +28,8 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (module->count_id(name) != 0) { - if (module->wires.count(name) > 0) - wire = module->wires.at(name); + if (module->wires_.count(name) > 0) + wire = module->wires_.at(name); if (wire != NULL && wire->width != width) wire = NULL; @@ -52,7 +52,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n wire->port_output = flag_output; if (flag_input || flag_output) { - wire->port_id = module->wires.size(); + wire->port_id = module->wires_.size(); module->fixup_ports(); } diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index df5a3d4b9..460dd9663 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -79,7 +79,7 @@ struct DeletePass : public Pass { RTLIL::Module *module = mod_it.second; if (flag_input || flag_output) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) { if (flag_input) it.second->port_input = false; @@ -95,7 +95,7 @@ struct DeletePass : public Pass { std::set delete_procs; std::set delete_mems; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) delete_wires.insert(it.second); diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 721d5c987..e163e7243 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -29,7 +29,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: if (module->count_id(to_name)) log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str()); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.first == from_name) { log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module)); module->rename(it.second, to_name); @@ -105,13 +105,13 @@ struct RenamePass : public Pass { continue; std::map new_wires; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (it.first[0] == '$' && design->selected(module, it.second)) do it.second->name = stringf("\\_%d_", counter++); while (module->count_id(it.second->name) > 0); new_wires[it.second->name] = it.second; } - module->wires.swap(new_wires); + module->wires_.swap(new_wires); std::map new_cells; for (auto &it : module->cells) { @@ -135,13 +135,13 @@ struct RenamePass : public Pass { continue; std::map new_wires; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (design->selected(module, it.second)) if (it.first[0] == '\\' && it.second->port_id == 0) it.second->name = NEW_ID; new_wires[it.second->name] = it.second; } - module->wires.swap(new_wires); + module->wires_.swap(new_wires); std::map new_cells; for (auto &it : module->cells) { diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 3380a935a..7e2b2fc9f 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -114,7 +114,7 @@ struct SccWorker SigPool selectedSignals; SigSet sigToNextCells; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) selectedSignals.add(sigmap(RTLIL::SigSpec(it.second))); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index e0f1a6d69..0cabdc06b 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -161,7 +161,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) } RTLIL::Module *mod = mod_it.second; - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (!lhs.selected_member(mod_it.first, it.first)) new_sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) @@ -215,11 +215,11 @@ static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs) SigMap sigmap(mod_it.second); SigPool selected_bits; - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (lhs.selected_member(mod_it.first, it.first)) selected_bits.add(sigmap(it.second)); - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (!lhs.selected_member(mod_it.first, it.first) && selected_bits.check_any(sigmap(it.second))) lhs.selected_members[mod_it.first].insert(it.first); } @@ -278,7 +278,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R if (lhs.selected_modules.count(mod->name) > 0) { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) lhs.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) lhs.selected_members[mod->name].insert(it.first); @@ -376,7 +376,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v RTLIL::Module *mod = mod_it.second; std::set selected_wires; - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0) selected_wires.insert(it.second); @@ -700,22 +700,22 @@ static void select_stmt(RTLIL::Design *design, std::string arg) RTLIL::Module *mod = mod_it.second; if (arg_memb.substr(0, 2) == "w:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "i:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (it.second->port_input && match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "o:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (it.second->port_output && match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "x:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else @@ -723,7 +723,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) size_t delim = arg_memb.substr(2).find(':'); if (delim == std::string::npos) { int width = atoi(arg_memb.substr(2).c_str()); - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (it.second->width == width) sel.selected_members[mod->name].insert(it.first); } else { @@ -731,7 +731,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) std::string max_str = arg_memb.substr(2+delim+1); int min_width = min_str.empty() ? 0 : atoi(min_str.c_str()); int max_width = max_str.empty() ? -1 : atoi(max_str.c_str()); - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (min_width <= it.second->width && (it.second->width <= max_width || max_width == -1)) sel.selected_members[mod->name].insert(it.first); } @@ -757,7 +757,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "a:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) @@ -777,7 +777,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else { if (arg_memb.substr(0, 2) == "n:") arg_memb = arg_memb.substr(2); - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (match_ids(it.first, arg_memb)) sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) @@ -1152,7 +1152,7 @@ struct SelectPass : public Pass { if (sel->selected_whole_module(mod_it.first) && list_mode) log("%s\n", id2cstr(mod_it.first)); if (sel->selected_module(mod_it.first)) { - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (sel->selected_member(mod_it.first, it.first)) LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); for (auto &it : mod_it.second->memories) @@ -1219,7 +1219,7 @@ struct SelectPass : public Pass { sel->optimize(design); for (auto mod_it : design->modules) if (sel->selected_module(mod_it.first)) { - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (sel->selected_member(mod_it.first, it.first)) total_count++; for (auto &it : mod_it.second->memories) @@ -1374,7 +1374,7 @@ struct LsPass : public Pass { if (design->modules.count(design->selected_active_module) > 0) { RTLIL::Module *module = design->modules.at(design->selected_active_module); - counter += log_matches("wires", pattern, module->wires); + counter += log_matches("wires", pattern, module->wires_); counter += log_matches("memories", pattern, module->memories); counter += log_matches("cells", pattern, module->cells); counter += log_matches("processes", pattern, module->processes); diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 8d98df719..0b4f2a8a2 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -111,7 +111,7 @@ struct SetattrPass : public Pass { if (!design->selected(module)) continue; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) do_setunset(it.second->attributes, setunset_list); diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index e26106103..82dc1d999 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -129,7 +129,7 @@ struct SetundefPass : public Pass { SigMap sigmap(module); SigPool undriven_signals; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (!it.second->port_input) undriven_signals.add(sigmap(it.second)); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index d63d98972..1feb90afb 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -305,7 +305,7 @@ struct ShowWorker std::set all_sources, all_sinks; std::map wires_on_demand; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (!design->selected_member(module->name, it.first)) continue; const char *shape = "diamond"; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 61de44066..691d972cf 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -149,7 +149,7 @@ struct SpliceWorker driven_bits.push_back(RTLIL::State::Sm); driven_bits.push_back(RTLIL::State::Sm); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_input) { RTLIL::SigSpec sig = sigmap(it.second); driven_chunks.insert(sig); @@ -175,7 +175,7 @@ struct SpliceWorker SigPool selected_bits; if (!sel_by_cell) - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) selected_bits.add(sigmap(it.second)); @@ -203,7 +203,7 @@ struct SpliceWorker std::vector> rework_wires; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (!no_outputs && it.second->port_output) { if (!design->selected(module, it.second)) continue; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 6bffba622..accb178ba 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -163,7 +163,7 @@ struct SplitnetsPass : public Pass { } else { - for (auto &w : module->wires) { + for (auto &w : module->wires_) { RTLIL::Wire *wire = w.second; if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second)) worker.splitmap[wire] = std::vector(); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 834770071..fabf1a73f 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -69,7 +69,7 @@ namespace STAT_INT_MEMBERS #undef X - for (auto &it : mod->wires) + for (auto &it : mod->wires_) { if (!design->selected(mod, it.second)) continue; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 55fe336f4..cb420f90a 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -173,11 +173,11 @@ struct FsmDetectPass : public Pass { } } - for (auto &wire_it : module->wires) + for (auto &wire_it : module->wires_) if (wire_it.second->port_id != 0) sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second))); - for (auto &wire_it : module->wires) + for (auto &wire_it : module->wires_) if (design->selected(module, wire_it.second)) detect_fsm(wire_it.second); } diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 51a4a75e7..85ff4af2a 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -283,10 +283,10 @@ static void extract_fsm(RTLIL::Wire *wire) // rename original state wire - module->wires.erase(wire->name); + module->wires_.erase(wire->name); wire->attributes.erase("\\fsm_encoding"); wire->name = stringf("$fsm$oldstate%s", wire->name.c_str()); - module->wires[wire->name] = wire; + module->wires_[wire->name] = wire; // unconnect control outputs from old drivers @@ -356,7 +356,7 @@ struct FsmExtractPass : public Pass { } std::vector wire_list; - for (auto &wire_it : module->wires) + for (auto &wire_it : module->wires_) if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none") if (design->selected(module, wire_it.second)) wire_list.push_back(wire_it.second); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 8c09d2eaa..a266c3445 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -221,15 +221,15 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla std::string portname = conn.first; if (portname.substr(0, 1) == "$") { int port_id = atoi(portname.substr(1).c_str()); - for (auto &wire_it : mod->wires) + for (auto &wire_it : mod->wires_) if (wire_it.second->port_id == port_id) { portname = wire_it.first; break; } } - if (mod->wires.count(portname) == 0) + if (mod->wires_.count(portname) == 0) log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); - int port_size = mod->wires.at(portname)->width; + int port_size = mod->wires_.at(portname)->width; if (conn_size == port_size) continue; if (conn_size != port_size*num) @@ -492,7 +492,7 @@ struct HierarchyPass : public Pass { } for (auto module : pos_mods) - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id > 0) pos_map[std::pair(module, wire->port_id)] = wire->name; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index e39f96ca8..774aabae1 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -212,7 +212,7 @@ struct SubmodWorker if (opt_name.empty()) { - for (auto &it : module->wires) + for (auto &it : module->wires_) it.second->attributes.erase("\\submod"); for (auto &it : module->cells) diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 32c7e63a0..4f1666533 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\D", data_reg_in.back()); std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); - if (module->wires.count(w_out_name) > 0) + if (module->wires_.count(w_out_name) > 0) w_out_name = genid(cell->name, "", i, "$q"); RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index df1a2697a..35a28d17d 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -137,7 +137,7 @@ struct MemoryShareWorker std::map> muxtree_upstream_map; std::set non_feedback_nets; - for (auto wire_it : module->wires) + for (auto wire_it : module->wires_) if (wire_it.second->port_output) { std::vector bits = RTLIL::SigSpec(wire_it.second); non_feedback_nets.insert(bits.begin(), bits.end()); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 63d03b205..9542e10df 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -52,7 +52,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) unused.insert(cell); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; if (wire->port_output || wire->get_bool_attribute("\\keep")) { std::set cell_list; @@ -175,12 +175,12 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (ct_all.cell_output(cell->type, it2.first)) direct_sigs.insert(assign_map(it2.second)); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (direct_sigs.count(assign_map(it.second)) || it.second->port_input) direct_wires.insert(it.second); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1); @@ -202,7 +202,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool used_signals_nodrivers.add(it2.second); } } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; if (wire->port_id > 0) { RTLIL::SigSpec sig = RTLIL::SigSpec(wire); @@ -219,7 +219,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } std::vector maybe_del_wires; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) { RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1; diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 672186006..290d4ffd9 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -45,7 +45,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) used_signals.add(sigmap(conn.second)); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (it.second->port_input) driven_signals.add(sigmap(it.second)); if (it.second->port_output) diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 8487152ff..16dedef58 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -136,7 +136,7 @@ struct OptMuxtreeWorker } } } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (it.second->port_output) for (int idx : sig2bits(RTLIL::SigSpec(it.second))) bit2info[idx].seen_non_mux = true; diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 8c09f5414..b26e8b37e 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -173,7 +173,7 @@ struct OptRmdffPass : public Pass { assign_map.set(mod_it.second); dff_init_map.set(mod_it.second); - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (it.second->attributes.count("\\init") != 0) dff_init_map.add(it.second, it.second->attributes.at("\\init")); mux_drivers.clear(); diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 4f733a373..c91f037d4 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -237,7 +237,7 @@ struct OptShareWorker assign_map.set(module); dff_init_map.set(module); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->attributes.count("\\init") != 0) dff_init_map.add(it.second, it.second->attributes.at("\\init")); diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 114f2567e..565d86a72 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -243,7 +243,7 @@ struct ProcArstPass : public Pass { if (!design->selected(mod_it.second, proc_it.second)) continue; proc_arst(mod_it.second, proc_it.second, assign_map); - if (global_arst.empty() || mod_it.second->wires.count(global_arst) == 0) + if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0) continue; std::vector arst_actions; for (auto sync : proc_it.second->syncs) @@ -266,7 +266,7 @@ struct ProcArstPass : public Pass { if (!arst_actions.empty()) { RTLIL::SyncRule *sync = new RTLIL::SyncRule; sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; - sync->signal = mod_it.second->wires.at(global_arst); + sync->signal = mod_it.second->wires_.at(global_arst); sync->actions = arst_actions; proc_it.second->syncs.push_back(sync); } diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 6949b76db..d4ff2a86c 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -87,16 +87,16 @@ struct BruteForceEquivChecker mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1) { log("Checking for equivialence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str()); - for (auto &w : mod1->wires) + for (auto &w : mod1->wires_) { RTLIL::Wire *wire1 = w.second; if (wire1->port_id == 0) continue; - if (mod2->wires.count(wire1->name) == 0) + if (mod2->wires_.count(wire1->name) == 0) log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str()); - RTLIL::Wire *wire2 = mod2->wires.at(wire1->name); + RTLIL::Wire *wire2 = mod2->wires_.at(wire1->name); if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output) log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str()); @@ -153,11 +153,11 @@ struct VlogHammerReporter ez.assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals)); - std::vector y_vec = satgen.importDefSigSpec(module->wires.at("\\y")); + std::vector y_vec = satgen.importDefSigSpec(module->wires_.at("\\y")); std::vector y_values; if (model_undef) { - std::vector y_undef_vec = satgen.importUndefSigSpec(module->wires.at("\\y")); + std::vector y_undef_vec = satgen.importUndefSigSpec(module->wires_.at("\\y")); y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end()); } @@ -252,7 +252,7 @@ struct VlogHammerReporter std::vector bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width); for (int i = 0; i < int(inputs.size()); i++) { - RTLIL::Wire *wire = module->wires.at(inputs[i]); + RTLIL::Wire *wire = module->wires_.at(inputs[i]); for (int j = input_widths[i]-1; j >= 0; j--) { ce.set(RTLIL::SigSpec(wire, j), bits.back()); recorded_set_vars.append(RTLIL::SigSpec(wire, j)); @@ -268,10 +268,10 @@ struct VlogHammerReporter } } - if (module->wires.count("\\y") == 0) + if (module->wires_.count("\\y") == 0) log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name)); - RTLIL::SigSpec sig(module->wires.at("\\y")); + RTLIL::SigSpec sig(module->wires_.at("\\y")); RTLIL::SigSpec undef; while (!ce.eval(sig, undef)) { @@ -318,9 +318,9 @@ struct VlogHammerReporter int width = -1; RTLIL::IdString esc_name = RTLIL::escape_id(name); for (auto mod : modules) { - if (mod->wires.count(esc_name) == 0) + if (mod->wires_.count(esc_name) == 0) log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name)); - RTLIL::Wire *port = mod->wires.at(esc_name); + RTLIL::Wire *port = mod->wires_.at(esc_name); if (!port->port_input || port->port_output) log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name)); if (width >= 0 && width != port->width) @@ -469,7 +469,7 @@ struct EvalPass : public Pass { } if (shows.size() == 0) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_output) shows.push_back(it.second->name); } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 21af63a36..c30e6e0c8 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -87,7 +87,7 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module *modu dffsignals.add(sigmap(it.second->get("\\Q"))); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (dffsignals.check_any(it.second)) dff_wires.insert(it.first); } @@ -161,7 +161,7 @@ static void create_dff_dq_map(std::map &map, RTLIL: } std::map empty_dq_map; - for (auto &it : module->wires) + for (auto &it : module->wires_) { if (!consider_wire(it.second, empty_dq_map)) continue; @@ -321,7 +321,7 @@ struct ExposePass : public Pass { for (auto &it : shared_dff_wires) { if (!dff_dq_maps[mod_it.second].count(it)) continue; - if (!compare_wires(first_module->wires.at(it), mod_it.second->wires.at(it))) + if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it))) continue; new_shared_dff_wires.insert(it); } @@ -365,7 +365,7 @@ struct ExposePass : public Pass { if (first_module == NULL) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module])) if (!flag_dff || dff_wires.count(it.first)) shared_wires.insert(it.first); @@ -385,16 +385,16 @@ struct ExposePass : public Pass { { RTLIL::Wire *wire; - if (module->wires.count(it) == 0) + if (module->wires_.count(it) == 0) goto delete_shared_wire; - wire = module->wires.at(it); + wire = module->wires_.at(it); if (!design->selected(module, wire)) goto delete_shared_wire; if (!consider_wire(wire, dff_dq_maps[module])) goto delete_shared_wire; - if (!compare_wires(first_module->wires.at(it), wire)) + if (!compare_wires(first_module->wires_.at(it), wire)) goto delete_shared_wire; if (flag_dff && !dff_wires.count(it)) goto delete_shared_wire; @@ -449,7 +449,7 @@ struct ExposePass : public Pass { SigMap out_to_in_map; - for (auto &it : module->wires) + for (auto &it : module->wires_) { if (flag_shared) { if (shared_wires.count(it.first) == 0) @@ -491,10 +491,10 @@ struct ExposePass : public Pass { for (auto &dq : dff_dq_maps[module]) { - if (!module->wires.count(dq.first)) + if (!module->wires_.count(dq.first)) continue; - RTLIL::Wire *wire = module->wires.at(dq.first); + RTLIL::Wire *wire = module->wires_.at(dq.first); std::set wire_bits_set = sigmap(wire).to_sigbit_set(); std::vector wire_bits_vec = sigmap(wire).to_sigbit_vector(); @@ -587,7 +587,7 @@ struct ExposePass : public Pass { { RTLIL::Module *mod = design->modules.at(cell->type); - for (auto &it : mod->wires) + for (auto &it : mod->wires_) { RTLIL::Wire *p = it.second; if (!p->port_input && !p->port_output) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index d5336ca01..5d23318ce 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -602,7 +602,7 @@ struct FreduceWorker int bits_full_total = 0; std::vector> batches; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_input) { batches.push_back(sigmap(it.second).to_sigbit_set()); bits_full_total += it.second->width; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 0c5989b10..248f934c5 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -73,13 +73,13 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Module *gold_module = design->modules.at(gold_name); RTLIL::Module *gate_module = design->modules.at(gate_name); - for (auto &it : gold_module->wires) { + for (auto &it : gold_module->wires_) { RTLIL::Wire *w1 = it.second, *w2; if (w1->port_id == 0) continue; - if (gate_module->wires.count(it.second->name) == 0) + if (gate_module->wires_.count(it.second->name) == 0) goto match_gold_port_error; - w2 = gate_module->wires.at(it.second->name); + w2 = gate_module->wires_.at(it.second->name); if (w1->port_input != w2->port_input) goto match_gold_port_error; if (w1->port_output != w2->port_output) @@ -91,13 +91,13 @@ static void create_miter_equiv(struct Pass *that, std::vector args, log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str()); } - for (auto &it : gate_module->wires) { + for (auto &it : gate_module->wires_) { RTLIL::Wire *w1 = it.second, *w2; if (w1->port_id == 0) continue; - if (gold_module->wires.count(it.second->name) == 0) + if (gold_module->wires_.count(it.second->name) == 0) goto match_gate_port_error; - w2 = gold_module->wires.at(it.second->name); + w2 = gold_module->wires_.at(it.second->name); if (w1->port_input != w2->port_input) goto match_gate_port_error; if (w1->port_output != w2->port_output) @@ -120,7 +120,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::SigSpec all_conditions; - for (auto &it : gold_module->wires) + for (auto &it : gold_module->wires_) { RTLIL::Wire *w1 = it.second; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 71eba2f7f..90c671165 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -94,7 +94,7 @@ struct SatHelper RTLIL::SigSpec big_lhs, big_rhs; - for (auto &it : module->wires) + for (auto &it : module->wires_) { if (it.second->attributes.count("\\init") == 0) continue; @@ -1158,19 +1158,19 @@ struct SatPass : public Pass { log_cmd_error("The options -set-init-undef, -set-init-def, and -set-init-zero are exclusive!\n"); if (set_def_inputs) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_input) sets_def.push_back(it.second->name); } if (show_inputs) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_input) shows.push_back(it.second->name); } if (show_outputs) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_output) shows.push_back(it.second->name); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 92bcafc00..813e0e3e1 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -271,7 +271,7 @@ namespace } // mark external signals (used in module ports) - for (auto &wire_it : mod->wires) + for (auto &wire_it : mod->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id > 0) @@ -300,7 +300,7 @@ namespace RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name); // create cell ports - for (auto &it : needle->wires) { + for (auto &it : needle->wires_) { RTLIL::Wire *wire = it.second; if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) @@ -742,7 +742,7 @@ struct ExtractPass : public Pass { std::vector chunks = sigmap(conn.second); for (auto &chunk : chunks) if (chunk.wire != NULL) - chunk.wire = newMod->wires.at(chunk.wire->name); + chunk.wire = newMod->wires_.at(chunk.wire->name); newCell->set(conn.first, chunks); } } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index ab3bb3ed0..6f7427f03 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -118,7 +118,7 @@ struct IopadmapPass : public Pass { if (!design->selected(module) || module->get_bool_attribute("\\blackbox")) continue; - for (auto &it2 : module->wires) + for (auto &it2 : module->wires_) { RTLIL::Wire *wire = it2.second; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index bee1df406..03aac6693 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -46,8 +46,8 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module if (chunk.wire != NULL) { std::string wire_name = chunk.wire->name; apply_prefix(prefix, wire_name); - assert(module->wires.count(wire_name) > 0); - chunk.wire = module->wires[wire_name]; + assert(module->wires_.count(wire_name) > 0); + chunk.wire = module->wires_[wire_name]; } sig = chunks; } @@ -72,7 +72,7 @@ struct TechmapWorker if (module == NULL) return result; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { const char *p = it.first.c_str(); if (*p == '$') continue; @@ -125,7 +125,7 @@ struct TechmapWorker std::map positional_ports; - for (auto &it : tpl->wires) { + for (auto &it : tpl->wires_) { if (it.second->port_id > 0) positional_ports[stringf("$%d", it.second->port_id)] = it.first; std::string w_name = it.second->name; @@ -145,12 +145,12 @@ struct TechmapWorker RTLIL::IdString portname = it.first; if (positional_ports.count(portname) > 0) portname = positional_ports.at(portname); - if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) { + if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) { if (portname.substr(0, 1) == "$") log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); continue; } - RTLIL::Wire *w = tpl->wires.at(portname); + RTLIL::Wire *w = tpl->wires_.at(portname); RTLIL::SigSig c; if (w->port_output) { c.first = it.second; @@ -265,7 +265,7 @@ struct TechmapWorker for (auto conn : cell->connections()) { if (conn.first.substr(0, 1) == "$") continue; - if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0) + if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0) continue; if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) goto next_tpl; @@ -388,7 +388,7 @@ struct TechmapWorker assert(!strncmp(q, "_TECHMAP_DO_", 12)); std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); - while (tpl->wires.count(new_name)) + while (tpl->wires_.count(new_name)) new_name += "_"; tpl->rename(data.wire, new_name);