From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Apr 2019 06:57:23 +0000 (+0100)
Subject: add in_multi and stage_ctl args to FIFOControl
X-Git-Tag: ls180-24jan2020~1224
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f997f92aae9a42a1482c6273a807c1e49fc0ab28;p=ieee754fpu.git

add in_multi and stage_ctl args to FIFOControl
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index fd6e9eab..96fb86f3 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -1100,7 +1100,8 @@ class FIFOControl(ControlBase):
         i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
     """
 
-    def __init__(self, depth, stage, fwft=True, buffered=False):
+    def __init__(self, depth, stage, in_multi=None, stage_ctl=False,
+                                     fwft=True, buffered=False):
         """ FIFO Control
 
             * depth: number of entries in the FIFO
@@ -1130,7 +1131,7 @@ class FIFOControl(ControlBase):
         self.fwft = fwft
         self.buffered = buffered
         self.fdepth = depth
-        ControlBase.__init__(self, stage=stage)
+        ControlBase.__init__(self, stage, in_multi, stage_ctl)
 
     def elaborate(self, platform):
         self.m = m = ControlBase._elaborate(self, platform)
@@ -1169,3 +1170,10 @@ class FIFOControl(ControlBase):
         m.d.comb += o_data
 
         return m
+
+"""
+class BufferedHandshake(FIFOControl):
+    def __init__(self, stage, in_multi=None, stage_ctl=False):
+        FIFOControl.__init__(self, 2, stage, in_multi, stage_ctl,
+                                   fwft=True, buffered=False)
+"""
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 27fb9b0b..794fd9d5 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -48,7 +48,7 @@ def check_o_n_valid2(dut, val):
 def tbench(dut):
     #yield dut.i_p_rst.eq(1)
     yield dut.n.i_ready.eq(0)
-    yield dut.p.o_ready.eq(0)
+    #yield dut.p.o_ready.eq(0)
     yield
     yield
     #yield dut.i_p_rst.eq(0)