From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 19 Feb 2019 22:20:04 +0000 (-0800)
Subject: Merge branch 'master' into xaig
X-Git-Tag: working-ls180~1237^2~304
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9af902532bcf44ddd0c5f0f28ac70880e5f2d07;p=yosys.git

Merge branch 'master' into xaig
---

f9af902532bcf44ddd0c5f0f28ac70880e5f2d07
diff --cc tests/tools/autotest.sh
index 0ffa062e3,6fdd1e80a..65fd4cb1f
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@@ -112,13 -133,10 +134,14 @@@ d
  		fn=$(basename $fn)
  		bn=$(basename $bn)
  
 +		if [[ "$ext" == "v" ]]; then
 +			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
 +		else
 +			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
 +			frontend="verilog"
 +		fi
+ 		rm -f ${bn}_ref.fir
  
 -		egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
 -
  		if [ ! -f ../${bn}_tb.v ]; then
  			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
  		else