From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 17:58:08 +0000 (-0500)
Subject: ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.
X-Git-Tag: stable_2012_02_02~1233
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9d1bba22a9e73ab45c0e255ca70eb509915181a;p=gem5.git

ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.
---

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index e2b73e2e2..903982f29 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -94,12 +94,14 @@ def operands {{
                maybePCRead, maybeIWPCWrite),
     'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
                 maybePCRead, maybeAIWPCWrite),
+    'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0),
     'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
              maybeAlignedPCRead, maybePCWrite),
     'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
               maybePCRead, maybePCWrite),
     'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
               maybePCRead, maybePCWrite),
+    'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 0),
     'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
               maybePCRead, maybePCWrite),
     'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,