From: lkcl Date: Sun, 7 Aug 2022 23:38:32 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~900 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9d5bb8140bd1dd930f848a53212c5648b994dbe;p=libreriscv.git --- diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index c3e31c8f6..397afdc7a 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -113,12 +113,12 @@ These are like a variant of `fmvfg` and `oris`, combined. Power ISA currently requires a large number of instructions to get Floating Point constants into registers. `fmvis` on its own is equivalent to BF16 to FP32/64 conversion, -but if followed up by `frlsi` an additional 16 bits of accuracy in the +but if followed up by `fishmv` an additional 16 bits of accuracy in the mantissa may be achieved. *IBM may consider it worthwhile to extend these two instructions to -v3.1 Prefixed (`pfmvis` and `pfrlsi`). If so it is recommended that -`pfmvis` load a full FP32 immediate and `pfrlsi` supplies the three high +v3.1 Prefixed (`pfmvis` and `pfishmv`). If so it is recommended that +`pfmvis` load a full FP32 immediate and `pfishmv` supplies the three high missing exponent bits (numbered 8 to 10) and the lower additional 29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.*