From: Luke Kenneth Casson Leighton Date: Wed, 19 Jun 2019 14:59:57 +0000 (+0100) Subject: add SV VLIW idea X-Git-Tag: convert-csv-opcode-to-binary~4597 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9df6e20711c87fb2f034d6618b40a5a8a476a4a;p=libreriscv.git add SV VLIW idea --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 8f6c98bf1..3d0838a78 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2230,8 +2230,9 @@ Optional VL/MAXVL/SubVL Block: Reminder of the variable-length format from Section 1.5 of the RISC-V ISA: -| .. | xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | -| -- | ---- | ---------------- | ---------------- | -------------------------- | +| base+4 | base+2 | base | number of bits | +| ------ | ---------------- | ---------------- | -------------------------- | +| ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | Notes: