From: lkcl <lkcl@web>
Date: Sun, 17 Jul 2022 12:25:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1168
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9efea92ac7399c08041b5f5381add497fa336b5;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 24589ead6..a4b1857df 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -7,6 +7,7 @@
 * <https://bugs.libre-soc.org/show_bug.cgi?id=697> Reduce Modes
 * <https://bugs.libre-soc.org/show_bug.cgi?id=864> parallel prefix simulator
 * <https://bugs.libre-soc.org/show_bug.cgi?id=809> OV sv.addex discussion
+* ARM SVE Fault-first <https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf>
 
 This is the appendix to [[sv/svp64]], providing explanations of modes
 etc. leaving the main svp64 page's primary purpose as outlining the