From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Feb 2020 00:08:04 +0000 (-0800)
Subject: Revert "abc9: fix abc9_arrival for flops"
X-Git-Tag: working-ls180~796
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9f86fd7582e447e2118534d888190ba14e39803;p=yosys.git

Revert "abc9: fix abc9_arrival for flops"

This reverts commit f7c0dbecee7ee8f2e3fc8bc8337e7045fd4aff15.
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 9b2bab95c..3cf36aca8 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -643,6 +643,7 @@ struct XAigerWriter
 			write_s_buffer(ff_bits.size());
 
 			for (const auto &i : ff_bits) {
+				const SigBit &d = i.first;
 				const Cell *cell = i.second;
 
 				int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
@@ -660,11 +661,7 @@ struct XAigerWriter
 					write_s_buffer(0);
 				}
 
-				auto it = cell->attributes.find(ID(abc9_arrival));
-				if (it != cell->attributes.end())
-					write_i_buffer(it->second.as_int());
-				else
-					write_i_buffer(0);
+				write_i_buffer(arrival_times.at(d, 0));
 				//write_o_buffer(0);
 			}
 
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index b26ea6720..8f5718411 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -254,19 +254,13 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 	SigMap sigmap(module);
 
-	dict<SigBit, Cell*> abc9_ff_d;
 	dict<SigBit, pool<IdString>> bit_drivers, bit_users;
 	TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
 	dict<IdString, std::vector<IdString>> box_ports;
 
 	for (auto cell : module->cells()) {
-		if (cell->type == "$__ABC9_FF_") {
-			auto d = sigmap(cell->getPort(ID(D)));
-			auto r = abc9_ff_d.insert(d);
-			log_assert(r.second);
-			r.first->second = cell;
+		if (cell->type == "$__ABC9_FF_")
 			continue;
-		}
 		if (cell->has_keep_attr())
 			continue;
 
@@ -363,7 +357,6 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 		IdString derived_type = box_module->derive(design, cell->parameters);
 		box_module = design->module(derived_type);
-		auto abc9_flop = box_module->get_bool_attribute("\\abc9_flop");
 
 		auto r = cell_cache.insert(derived_type);
 		auto &holes_cell = r.first->second;
@@ -402,7 +395,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 				// For flops only, create an extra 1-bit input that drives a new wire
 				//   called "<cell>.abc9_ff.Q" that is used below
-				if (abc9_flop) {
+				if (box_module->get_bool_attribute("\\abc9_flop")) {
 					box_inputs++;
 					Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
 					if (!holes_wire) {
@@ -432,28 +425,6 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 				holes_module->connect(holes_wire, holes_cell->getPort(port_name));
 			else // blackbox
 				holes_module->connect(holes_wire, Const(State::S0, GetSize(w)));
-
-			// Transfer abc9_arrival value from flop box output to $__ABC9_FF_ cell
-			if (abc9_flop) {
-				auto it = w->attributes.find(ID(abc9_arrival));
-				if (it == w->attributes.end())
-					continue;
-				auto jt = cell->connections_.find(port_name);
-				if (jt == cell->connections_.end())
-					continue;
-				auto kt = abc9_ff_d.find(jt->second);
-				if (kt == abc9_ff_d.end())
-					continue;
-#ifndef NDEBUG
-				if (ys_debug(1)) {
-					static std::set<std::pair<IdString,IdString>> seen;
-					if (seen.emplace(cell->type, port_name).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(port_name), it->second.as_int());
-				}
-#endif
-				auto r = kt->second->attributes.insert(ID(abc9_arrival));
-				log_assert(r.second);
-				r.first->second = it->second;
-			}
 		}
 	}
 }