From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Mon, 25 Mar 2019 20:18:55 +0000 (-0700)
Subject: synth_xilinx to use shregmap with -minlen 3
X-Git-Tag: yosys-0.9~171^2~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9fb05cf6684d855ce2fc776a20cd5552a4ef4a8;p=yosys.git

synth_xilinx to use shregmap with -minlen 3
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5237cc4c6..b6225a1a3 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -114,7 +114,7 @@ struct SynthXilinxPass : public Pass
 		log("        dff2dffe\n");
 		log("        opt -full\n");
 		log("        simplemap t:$dff* (only without -nosrl)\n");
-		log("        shregmap -tech xilinx (only without -nosrl)\n");
+		log("        shregmap -tech xilinx -minlen 3 (only without -nosrl)\n");
 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
 		log("        opt -fast\n");
 		log("\n");
@@ -267,7 +267,7 @@ struct SynthXilinxPass : public Pass
 
 			if (!nosrl) {
 				Pass::call(design, "simplemap t:$dff*");
-				Pass::call(design, "shregmap -tech xilinx");
+				Pass::call(design, "shregmap -tech xilinx -minlen 3");
 			}
 
 			if (vpr) {